Epitaxial wafer and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9873954-B2
Application number	US-201314406070-A
Country	US
Kind code	B2
Filing date	Oct 29, 2013
Priority date	Oct 31, 2012
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Provided are an epitaxial wafer and a method of fabricating the same. The method includes a pre-growth step of injecting a reaction source for epitaxial growth on a semiconductor wafer prepared in a chamber and growing an epitaxial layer by a predetermined first thickness at a predetermined first growth rate and at a predetermined first growth temperature, a heat treatment step of performing heat treatment on the epitaxial layer grown by the pre-growth step during a predetermined time, and a subsequent growth step of injecting the reaction source on the heat-treated semiconductor wafer and growing the epitaxial layer to a target thickness at a predetermined second growth rate and at a predetermined second growth temperature. The first growth rate is smaller than the second growth rate.

First claim

The invention claimed is:

1. A method of fabricating an epitaxial wafer, comprising:
a pre-growth step of injecting a reaction source for epitaxial growth on a semiconductor wafer prepared in a chamber and growing a first epitaxial layer by a predetermined first thickness at a predetermined first growth rate, at a predetermined first growth time and at a predetermined first growth temperature;
a heat treatment step of performing heat treatment on the first epitaxial layer to increase uniformity of a dopant of the first epitaxial layer; and
a subsequent growth step of injecting the reaction source on the heat-treated semiconductor wafer and growing a second epitaxial layer to a target thickness at a predetermined second growth rate, at a predetermined second growth time and at a predetermined second growth temperature,
wherein the first growth rate is smaller than the second growth rate and the first growth temperature is lower than the second growth temperature to decrease dislocation density of the first epitaxial layer,
wherein the first growth time is shorter than the second growth time,
wherein the first growth rate is set to 5 μm/h or less and the second growth rate is set to 20 μm/h or more,
wherein the first growth temperature is set, within a range of 1400° C. to 1500° C. and the second growth temperature is set within a range of 1500° C. to 1700° C.,
wherein the heat treatment step is inserted, between the pre-growth step growing the first epitaxial layer on the semiconductor wafer and the subsequent growth step growing the second epitaxial layer on the first epitaxial layer,
wherein a thickness of the second epitaxial layer is larger than the first thickness,
wherein the first and the second epitaxial layers have the same dopant, and
wherein a heat-treatment temperature in the heat treatment step is higher than the first growth temperature and is the same as the second growth temperature which is set within a range of 1500° C. to 1700° C.

2. The method of claim 1 , wherein the semiconductor wafer is a silicon carbide wafer and the reaction, source is a solid, liquid, or gaseous material including carbon and silicon.

Assignees

• Lg Innotek Co Ltd

Inventors

• Kang Seok Min

Classifications

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/2904 Primary

  Silicon carbide · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/20 Primary

  of semiconductor materials · CPC title

• C30B25/20 Primary

  the substrate being of the same materials as the epitaxial layer · CPC title