Multilayer electronic component

Patent metadata

Field	Value
Publication number	US-9871500-B2
Application number	US-201615082513-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	May 28, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A multilayer electronic component includes a stack and a balun. The stack includes a plurality of stacked dielectric layers and conductor layers. The balun is formed using the stack. The balun includes an unbalanced transmission line and first to fourth balanced transmission lines. The unbalanced transmission line includes a first line portion and a second line portion connected in series. The first and second balanced transmission lines are configured to be electromagnetically coupled to the first line portion. The third and fourth balanced transmission lines are configured to be electromagnetically coupled to the second line portion.

First claim

What is claimed is:

1. A multilayer electronic component comprising:
a stack;
a balun formed using the stack; and
a branching circuit that is formed using the stack and connected to the balun, wherein
the stack includes a plurality of dielectric layers and a plurality of conductor layers stacked on each other,
the balun includes:
an unbalanced port;
a first balanced port;
a second balanced port;
an unbalanced transmission line including a first line portion and a second line portion connected in series;
a first balanced transmission line and a second balanced transmission line configured to be electromagnetically coupled to the first line portion; and
a third balanced transmission line and a fourth balanced transmission line configured to be electromagnetically coupled to the second line portion;

each of the first and second line portions and first to fourth balanced transmission lines has a first end and a second end opposite to each other,
the first end of the first line portion is connected to the unbalanced port,
the second end of the first line portion is connected to the second end of the second line portion,
the first end of the first balanced transmission line and the first end of the second balanced transmission line are connected to the first balanced port,
the first end of the third balanced transmission line and the first end of the fourth balanced transmission line are connected to the second balanced port,
each of the first and second line portions and first to fourth balanced transmission lines is formed using at least one of the plurality of conductor layers,
the branching circuit includes a first filter and a second filter connected to the unbalanced port,
the first filter selectively passes a first signal of a frequency within a first frequency band, and
the second filter selectively passes a second signal of a frequency within a second frequency band higher than the first frequency band.

2. The multilayer electronic component according to claim 1 , wherein
the first line portion, the first balanced transmission line, and the second balanced transmission line are at locations different from each other in a direction in which the plurality of dielectric layers are stacked, the first line portion being interposed between the first balanced transmission line and the second balanced transmission line, and
the second line portion, the third balanced transmission line, and the fourth balanced transmission line are at locations different from each other in the direction in which the plurality of dielectric layers are stacked, the second line portion being interposed between the third balanced transmission line and the fourth balanced transmission line.

3. The multilayer electronic component according to claim 2 , wherein each of the first and second line portions and first to fourth balanced transmission lines includes a coil.

4. The multilayer electronic component according to claim 1 , wherein
the first line portion, the first balanced transmission line, and the second balanced transmission line are located in a first region in the stack,
the second line portion, the third balanced transmission line, and the fourth balanced transmission line are located in a second region in the stack, and
the first region and the second region are separate from each other in a direction in which the plurality of dielectric layers are stacked.

Assignees

• Tdk Corp

Inventors

• Tsutsumi Masanori
• Tsukamoto Kazuhiro
• Kitami Manabu
• TAKAMI Toshiyuki
• Kusumoto Shohei
• Hirabayashi Noriyuki

Classifications

• H03H7/42 Primary

  Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns · CPC title

• H01P5/1022 Primary

  Transitions to dielectric waveguide · CPC title