Semiconductor device and an electronic apparatus

Patent metadata

Field	Value
Publication number	US-9871031-B2
Application number	US-201514934949-A
Country	US
Kind code	B2
Filing date	Nov 6, 2015
Priority date	Nov 7, 2014
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A semiconductor device includes a P-type substrate, and an N-well in the P-type substrate. A first N+ diffusion region is located in the P-type substrate, and a first P+ diffusion region is located in the N-well. A second P+ diffusion region is located across a boundary between the P-type substrate and the N-well. A first gate electrode overlies the N-well between the first P+ diffusion regions and the second P+ diffusion region. A second gate electrode overlies the P-type substrate between the second P+ diffusion region and the first N+ diffusion region. The first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device. The first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS transistor. The second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a P-type substrate;
an N-well in the P-type substrate;
a first N+ diffusion region in the P-type substrate;
a first P+ diffusion region in the N-well;
a second P+ diffusion region located across a boundary between the P-type substrate and the N-well;
a third P+ diffusion region in the P-type substrate;
a first gate electrode overlying the N-well between the first P+ diffusion regions and the second P+ diffusion region;
a second gate electrode overlying the P-type substrate between the second P+ diffusion region and the first N+ diffusion region and connected to the third P+ diffusion region, and both being connected to a ground pad;
wherein the first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS structure;
wherein the second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode structure; and
wherein the first gate electrode is connected to the first P+ diffusion region, and both are connected to an input/output (IO) pad.

2. The device of claim 1 , wherein the first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device.

3. The device of claim 1 , wherein the second gate electrode is connected to the first N+ diffusion region.

4. The device of claim 1 , further comprising a second N+ diffusion region in a surface region of the N-type well.

5. The device of claim 4 , wherein the second N+ diffusion region is coupled to the IO pad.

6. The device of claim 1 , further comprising a high-k dielectric metal gate transistor.

7. An electronic device, comprising:
a P-type substrate;
an N-well in the P-type substrate;
a first N+ diffusion region in the P-type substrate;
a first P+ diffusion region in the N-well;
a second P+ diffusion region located across a boundary between the P-type substrate and the N-well;
a third P+ diffusion region in the P-type substrate;
a first gate electrode overlying the N-well between the first P+ diffusion regions and the second P+ diffusion region;
a second gate electrode overlying the P-type substrate between the second P+ diffusion region and the first N+ diffusion region and connected to the third P+ diffusion region, and both being connected to a ground pad;
wherein the first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device;
wherein the first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS structure;
wherein the second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode structure; and
wherein the first gate electrode, the first P+ diffusion region, and the second N+ diffusion region are coupled to an input/output (TO) pad.

8. The device of claim 7 , further comprising a second N+ diffusion region in a surface region of the N-type well.

9. The device of claim 7 , wherein the second gate electrode is connected to the first N+ diffusion region.

10. An electronic apparatus, comprising a semiconductor device and an electronic assembly connected to said semiconductor device, wherein the semiconductor device comprises:
a P-type substrate;
an N-well in the P-type substrate;
a first N+ diffusion region in the P-type substrate;
a first P+ diffusion region in the N-well;
a second P+ diffusion region located across a boundary between the P-type substrate and the N-well;
a third P+ diffusion region in the P-type substrate;
a first gate electrode overlying the N-well between the first P+ diffusion region and the second P+ diffusion region;
a second gate electrode overlying the P-type substrate between the second P+ diffusion region and the first N+ diffusion region and connected to the third P+ diffusion region, and both being connected to a ground pad;
wherein the first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device;
wherein the first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS structure;
wherein the second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode structure; and
wherein the first gate electrode, the first P+ diffusion region, and the second N+ diffusion region are coupled to an input/output (IO) pad.

11. The apparatus of claim 10 , wherein the semiconductor device further comprises a second N+ diffusion region in a surface region of the N-type well.

12. The apparatus of claim 10 , wherein the second gate electrode is connected to the first N+ diffusion region.

13. The apparatus of claim 10 , wherein the semiconductor device further comprises a high-k metal gate transistor.

Assignees

• Semiconductor Mfg International (Shanghai) Corporation

Inventors

• Liu Yi
• Wang Jun
• Ma Ying
• Lu Bin
• Cheng Huijuan

Classifications

• H01L29/6609

  Electricity · mapped topic

• H01L29/87

  Electricity · mapped topic

• H01L27/0262 Primary

  Electricity · mapped topic

• H01L29/7436

  Electricity · mapped topic

• H01L27/0277

  Electricity · mapped topic