Semiconductor device having mesh-patterned wirings

Patent metadata

Field	Value
Publication number	US-9871027-B2
Application number	US-201514821187-A
Country	US
Kind code	B2
Filing date	Aug 7, 2015
Priority date	Sep 2, 2014
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A semiconductor device includes a mesh-patterned power source wiring that supplies respective circuits with a power source voltage supplied to a plurality of locations at an outer periphery of the semiconductor device. The semiconductor device also includes a back-biasing wiring supplying, to a semiconductor substrate, a substrate voltage that controls a threshold voltage of a semiconductor element. The back-biasing wiring includes a upper layer mesh wiring that receives a supply of a substrate voltage, and a lower layer mesh wiring that is provided in a different wiring layer from the upper layer mesh wiring. The outer peripheries of the upper layer mesh wiring and the lower layer mesh wiring are connected to each other through plural vias.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of circuits that are provided on a semiconductor substrate, and that each include a semiconductor element having a threshold voltage, the threshold voltage controlled by a substrate voltage supplied to the semiconductor substrate;
a mesh-patterned first wiring that is formed by arranging a plurality of wirings extending in mutually different directions so as to intersect with each other, and that supplies each of the plurality of circuits with a power source voltage supplied to a plurality of locations at an outer periphery of the first wiring;
a mesh-patterned second wiring that is formed by arranging a plurality of wirings extending in mutually different directions so as to intersect with each other, and that is provided at a wiring layer, and that receives a supply of the substrate voltage; and
a mesh-patterned third wiring that is formed by arranging a plurality of wirings extending in mutually different directions so as to intersect with each other, and that is provided at a different wiring layer from the wiring layer at which the second wiring is provided, that has an outer periphery connected to an outer periphery of the second wiring, and that supplies the substrate voltage received from the second wiring to the semiconductor substrate.

2. The semiconductor device of claim 1 , wherein the substrate voltage is supplied to a central portion of the second wiring.

3. The semiconductor device of claim 1 , wherein the second wiring and the third wiring are configured such that a drop in an absolute value of the substrate voltage in a portion corresponding to a first region, where power consumption by circuits of the plurality of circuits is relatively high in the semiconductor device, is greater than a drop in an absolute value of the substrate voltage in a portion corresponding to a second region, where power consumption by circuits of the plurality of circuits is less than in the first region.

4. The semiconductor device of claim 3 , wherein:
the outer peripheries of the second wiring and the third wiring are connected to each other through a plurality of vias; and
a formation density of vias of the plurality of vias in the portion corresponding to the first region is lower than a formation density of vias of the plurality of vias in the portion corresponding to the second region.

5. The semiconductor device of claim 3 , wherein, in the third wiring, a wiring width at the portion corresponding to the first region is less than a wiring width at the portion corresponding to the second region.

6. The semiconductor device of claim 1 , further comprising a voltage generation section that generates the substrate voltage.

7. The semiconductor device of claim 1 , wherein the outer peripheries of the second wiring and the third wiring are connected to each other through a plurality of vias.

8. The semiconductor device of claim 7 , wherein the plurality of vias are disposed at uniform intervals.

9. The semiconductor device of claim 1 , wherein the third wiring is not connected to the second wiring except at the outer periphery of the second wiring.

Assignees

• Socionext Inc

Inventors

• Kondo Eiji

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H01L23/5226

  Electricity · mapped topic

• G11C5/146

  Substrate bias generators (G11C5/141 takes precedence) · CPC title