Multi-level chip interconnect

Patent metadata

Field	Value
Publication number	US-9871017-B2
Application number	US-201614986727-A
Country	US
Kind code	B2
Filing date	Jan 4, 2016
Priority date	Jan 4, 2016
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.

First claim

What is claimed is:

1. A multi-layered integrated circuit (IC), comprising: a first conductive layer comprising a first material;
a first contact terminal coupled to the first conductive layer;
a second conductive layer disposed over the first conductive layer, the second conductive layer comprising a second material;
a second contact terminal coupled to the second conductive layer;
at least one opening in the second conductive layer, the first contact terminal externally accessible via the at least one opening in the second conductive layer, such that the first contact terminal and the second contact terminal are concurrently externally accessible; and
a protective covering enclosing the first and second conductive layers and including one or more openings in the protective covering for electrical access to at least one of the first and second contact terminals.

2. The multi-layered IC of claim 1 , wherein the protective covering comprises a passivation layer.

3. The multi-layered IC of claim 1 , further comprising a third conductive layer disposed below the first and second conductive layers, and further comprising one or more openings in the first and second conductive layers for electrical access to at least one contact at the third conductive layer with contact terminals.

4. The multi-layered IC of claim 1 , wherein at least one of the first and second contact terminals protrudes through an opening in the protective covering, and is arranged to be electrically coupled to a circuit external to the IC.

5. The multi-layered IC of claim 4 , wherein the first contact terminal is comprised of a first material set and has a package geometry compatible to the circuit external to the IC, and wherein the second contact terminal is arranged to be concurrently electrically coupled to a second circuit external to the IC and is comprised of a second material set and has a geometry compatible to the second circuit external to the IC.

6. The multi-layered IC of claim 1 , further comprising an insulating layer disposed between at least a portion of the first conductive layer and the second conductive layer.

7. The multi-layered IC of claim 1 , further comprising one or more vias coupled to the first conductive layer and/or the second conductive layer and extending to a lower layer of the IC.

8. The multi-layered IC of claim 1 , wherein the first contact terminal protrudes through the at least one opening in the second conductive layer without making contact to the second conductive layer.

9. The multi-layered IC of claim 1 , wherein the first material is the same as the second material.

10. The multi-layered IC of claim 1 , wherein the first material is different than the second material.

11. The multi-layered IC of claim 10 , wherein the first conductive layer comprises a metallization layer of a first metal and the second conductive layer comprises a metallization layer of a second, different metal.

12. The multi-layered IC of claim 1 , wherein the first contact terminal and the second contact terminal are comprised of different materials, the first contact terminal being comprised of a material compatible to the first material of the first conductive layer and the second contact terminal being comprised of a material compatible to the second material of the second conductive layer.

13. The multi-layered IC of claim 1 , wherein a portion of the first conductive layer is electrically coupled to a portion of the second conductive layer.

14. The multi-layered IC of claim 1 , wherein the first contact terminal comprises a flip chip bump contact.

15. The multi-layered IC of claim 1 , wherein the second contact terminal comprises a wafer test point.

16. A multi-layered integrated circuit (IC), comprising: a first layer comprising copper traces;
at least one copper contact terminal coupled to the first layer;
a second layer comprising aluminum-alloy traces, disposed over the first layer; at least one aluminum-alloy contact terminal coupled to the second layer; and
at least one opening in the second layer, a copper contact terminal coupled to the first layer protruding through the at least one opening in the second layer without making contact with the second layer, the copper contact terminal and the aluminum-alloy contact terminal arranged to be concurrently electrically coupled to one or more circuits external to the IC.

17. A multi-layered chip die, comprising:
a plurality of metallic layers arranged in a stack, and including electrical contact nodes;
a top level disposed over the stack, and having multiple terminal pads for electrically coupling the chip die to an external system; and
multiple interconnects electrically coupling the electrical contact nodes of respective layers of the plurality of metallic layers to individual terminal pads at the top level, without making contact with other layers of the plurality of metallic layers of the chip die.

18. The multi-layered chip die of claim 17 , further comprising one or more openings in the top level and one or more openings in at least one layer of the plurality of metallic layers arranged to provide electrical access to one or more electrical contact nodes on one or more metallic layers below the at least one layer.

19. The multi-layered chip die of claim 17 , wherein at least one layer of the plurality of metallic layers and at least one included contact node is comprised of copper and at least one other layer of the plurality of metallic layers and at least one other included contact node is comprised of an aluminum alloy.

20. The multi-layered chip die of claim 17 , wherein the multi-layered chip die comprises a flip-chip packaged integrated circuit (IC).

21. A multi-layered integrated circuit (IC), comprising:
a first conductive layer comprising a first material;
a first contact terminal coupled to the first conductive layer;
a second conductive layer disposed over the first conductive layer, the second conductive layer comprising a second material;
a second contact terminal coupled to the second conductive layer; and
at least one opening in the second conductive layer, the first contact terminal externally accessible via the at least one opening in the second conductive layer, such that the first contact terminal and the second contact terminal are concurrently externally accessible, wherein the first contact terminal protrudes through the at least one opening in the second conductive layer without making contact to the second conductive layer.

22. A multi-layered integrated circuit (IC), comprising:
a first conductive layer comprising a first material;
a first contact terminal coupled to the first conductive layer;
a second conductive layer disposed over the first conductive layer, the second conductive layer comprising a second material;
a second contact terminal coupled to the second conductive layer; and
at least one opening in the second conductive layer, the first contact terminal externally accessible via the at least one opening in the second conductive layer, such that the first contact terminal and the second contact terminal are concurrently externally accessible, wherein the first material is different than the second material.

23. The multi-layered IC of claim 22 , wherein the first conductive layer comprises a metallization layer of a first metal and the second conductive layer comprises a metallization layer of a second, different metal.

24. A method, comprisin

Assignees

• Infineon Technologies Ag

Inventors

• Ossimitz Peter
• Jacobs Tobias

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title