Contact area design for solder bonding

Patent metadata

Field	Value
Publication number	US-9871013-B2
Application number	US-201414584748-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Dec 29, 2014
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

First claim

What is claimed is:

1. A package comprising:
a first package component comprising:
a first dielectric layer;
a second dielectric layer over and contacting the first dielectric layer;
a metal pad over the first dielectric layer, wherein the metal pad is in the second dielectric layer; and
a first plurality of openings in the metal pad, wherein the first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region;
a solder region in contact with the metal pad, wherein an outer edge of the solder region is in contact with a sidewall of the second dielectric layer; and
a metal trace in the first dielectric layer, the metal trace comprising a second plurality of openings filled with a dielectric material.

2. The package of claim 1 further comprising:
a second package component comprising a metal pillar.

3. The package of claim 1 , wherein
the metal trace comprises an edge vertically aligned with the metal pad, wherein a bottom surface of the metal pad is in contact with a top surface of the metal trace.

4. The package of claim 1 , wherein the metal trace comprises:
a trace portion having a first width, wherein the trace portion extends laterally beyond edges of the metal pad from a plan view; and
a pad portion having a second width greater than the first width, wherein the metal pad overlies and contacts the pad portion of the metal trace.

5. The package of claim 4 , wherein the pad portion of the metal trace is a solid pad with no opening therein.

6. The package of claim 4 , wherein the pad portion of the metal trace comprises the second plurality of openings, and bottom surfaces of the solder region contacts top surfaces of the dielectric material in the second plurality of openings.

7. The package of claim 6 , wherein each of the second plurality of openings is overlapped by one of the first plurality of openings.

8. The package of claim 1 further comprising a second dielectric layer comprising a portion at a same level as the metal pad, wherein the second dielectric layer comprises a top surface higher than a top surface of the metal pad.

9. The package of claim 1 , wherein a top surface of the first dielectric layer is exposed.

10. A package comprising:
a first package component comprising:
a metal trace; and
a metal pad over the metal trace, wherein the metal pad comprises a plurality of discrete portions physically separated from each other, wherein the plurality of discrete portions is electrically coupled to each other through the metal trace.

11. The package of claim 10 wherein bottoms of the plurality of discrete portions of the metal pad are in contact with a dielectric material, and edges of the plurality of discrete portions of the metal pad are vertically aligned to respective edges of corresponding portions of dielectric material.

12. The package of claim 10 further comprising:
a solder region physically contacting one of the plurality of discrete portions of the metal pad, and physically disconnected from remaining ones of the plurality of discrete portions of the metal pad; and
a via interconnecting the plurality of discrete portions of the metal pad.

13. The package of claim 10 further comprising a continuous solder region joining the plurality of discrete portions of the metal pad.

14. The package of claim 10 , wherein the metal trace comprises:
a trace portion having a first width, wherein the trace portion laterally extends beyond edges of the metal pad in a plan view; and
a pad portion having a second width greater than the first width, wherein the metal pad overlies and contacts the pad portion of the metal trace.

15. The package of claim 14 , wherein the pad portion of the metal trace is a solid pad with no opening therein.

16. The package of claim 10 , wherein the plurality of discrete portions are fully separated from each other without being interconnected by other portions of the metal pad.

17. The package of claim 10 , wherein an entirety of a bottom surface of the metal pad is in contact with a top surface of the metal trace.

18. A package comprising:
a first package component comprising:
a metal trace comprising a trace portion and a pad portion connected to the trace portion, wherein the pad portion is wider than the trace portion in a top view of the first package component;
a metal pad overlapping and in contact with the pad portion, wherein the trace portion and the pad portion are in a same metal layer, and the trace portion of the metal trace extends beyond edges of the metal pad in a plan view; and
a first plurality of openings in the metal pad, wherein the first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region, the first plurality of openings being wider at a region more distal from the metal trace than at a region more proximate to the metal trace;

a second package component; and
a solder region bonding the second package component to the metal pad.

19. The package of claim 18 , wherein the first plurality of openings comprises through-openings penetrating through the metal pad.

20. The package of claim 18 , wherein the pad portion of the metal trace comprises a second plurality of openings, with the second plurality of openings filled with a dielectric material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Pei-Chun
• Chen Yu-Feng
• Kuo Tin-Hao
• Chen Chen-Shien
• Huang Yu-Chih
• Wu Sheng-Yu

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title