Double-sided segmented line architecture in 3D integration

Patent metadata

Field	Value
Publication number	US-9870979-B2
Application number	US-201514833192-A
Country	US
Kind code	B2
Filing date	Aug 24, 2015
Priority date	Dec 30, 2013
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

First claim

What is claimed is:

1. A structure, comprising:
one or more intra-wafer through substrate vias (TSVs) extending from a front side of a substrate of a first integrated circuit (IC) chip to a back side of the substrate of the first IC chip;
a local architecture in a front side wiring layer of the first IC chip, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs;
a global architecture in a back side wiring layer of the first IC chip, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together, wherein the global architecture comprises a signal global word line;
a second IC chip bonded to the first IC chip, the second IC chip comprising a front side wiring layer and a back side wiring layer; and
one or more inter-wafer TSVs continuously extending through an entire thickness of a periphery of the first IC chip and an entire thickness of a periphery of the second IC chip, the one or more inter-wafer TSVs electrically connecting the back side wiring layer of the second IC chip to the back side wiring layer of the first IC chip.

2. The structure of claim 1 , wherein the local architecture in the front side wiring layer of the first IC chip comprises:
a global decoder circuit;
a local word line driver circuit; and
a local word line connected to the local word line driver circuit and a memory cell.

3. The structure of claim 1 , wherein the one or more local features in the local architecture are connected to an individual wire in the global architecture by an individual intra-wafer TSV, the thickness of an individual wire in the global architecture being approximately 8 times to approximately 10 times larger than the thickness of an individual wire in the local architecture.

4. The structure of claim 1 , wherein the one or more inter-wafer TSVs have a width that is approximately 1.25 times to approximately 30 times larger than a width of the one or more intra-wafer TSVs.

5. A structure, comprising:
one or more intra-wafer through substrate vias (TSVs) extending from a front side of a substrate of a first integrated circuit (IC) chip to a back side of the substrate of the first IC chip;
a local architecture comprising a global decoder circuit, a local word line driver circuit, and a local word line connected to the local word line driver circuit and a memory cell, the local architecture located on a front side wiring layer on the front side of the substrate of the first IC chip, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs;
a second IC chip bonded to the front side wiring layer of the first IC chip, the second IC chip comprising a front side wiring layer and a back side wiring layer;
a global architecture comprising a signal global word line, the global architecture located on a back side wiring layer on the back side of the substrate of the first IC chip, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together; and
one or more inter-wafer TSVs continuously extending through an entire thickness of both the first IC chip and the second IC chip along a periphery of both the first IC chip and the second IC chip, the one or more inter-wafer TSVs comprising a conductive material and electrically connecting the back side wiring layer of the second IC chip to the back side wiring layer of the first IC chip, the one or more inter-wafer TSVs have a width that is approximately 1.25 times to approximately 30 times larger than a width of the one or more intra-wafer TSVs.

6. The structure of claim 5 , wherein the one or more local features in the local architecture are connected to an individual wire in the global architecture by an individual intra-wafer TSV, the thickness of an individual wire in the global architecture being approximately 8 times to approximately 10 times larger than the thickness of an individual wire in the local architecture.

7. A structure, comprising:
one or more intra-wafer through substrate vias (TSVs) extending from a front side of a substrate of a first integrated circuit (IC) chip to a back side of the substrate of the first IC chip;
a local architecture in a front side wiring layer of the first IC chip, the local architecture comprising a global decoder circuit, a local word line driver circuit, and a local word line connected to the local word line driver circuit and a memory cell, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs;
a second IC chip bonded to the first IC chip, the second IC chip comprising a front side wiring layer and a back side wiring layer, wherein the one or more intra-wafer TSVs in the back side of the substrate of the first IC chip are exposed such that a conductive path exist through an entire thickness of the substrate of the first IC chip;
a global architecture in a back side wiring layer of the first IC chip, the global architecture comprising a signal global word line, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together, wherein the one or more local features in the local architecture are connected to an individual wire in the global architecture by an individual intra-wafer TSV, the thickness of an individual wire in the global architecture being approximately 8 times to approximately 10 times larger than the thickness of an individual wire in the local architecture; and
one or more inter-wafer TSVs continuously extending through an entire thickness of the first IC chip and through an entire thickness of the second IC chip, the one or more inter-wafer TSVs located along a periphery of both the first IC chip and the second IC chip, the one or more inter-wafer TSVs electrically connecting the back side wiring layer of the second IC chip to the back side wiring layer of the first IC chip, the one or more inter-wafer TSVs having a width that is approximately n times larger than a width of the one or more intra-wafer TSVs, the value of n varying between approximately 1.25 and approximately 30.

Assignees

• IBM

Inventors

• Batra Pooja R
• Golz John W
• Jacunski Mark
• Kirihata Toshiaki

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title