Plurality of seals for integrated device package

Patent metadata

Field	Value
Publication number	US-9870967-B2
Application number	US-201615066397-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Mar 10, 2016
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a substrate, a wall attached to the substrate, a first adhesive layer disposed between a bottom surface of the wall and a top surface of the substrate, and a second adhesive layer disposed around an outer perimeter of the first adhesive layer, the second adhesive layer disposed adjacent and contacting the wall, the second adhesive layer different from the first adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer connects the wall to electrical ground.

First claim

We claim:

1. A semiconductor package comprising:
a substrate;
a wall attached to the substrate;
a first electrically conductive adhesive layer comprising a first epoxy comprising a conductive filler disposed between a bottom surface of the wall and a top surface of the substrate; and
a second adhesive layer comprising a second epoxy different from the first epoxy, the second epoxy disposed around an outer perimeter of the first adhesive layer, the second adhesive layer disposed adjacent and contacting the wall, the second adhesive layer comprising a material that is different from the first adhesive layer,
wherein at least one of the first adhesive layer and the second adhesive layer connects the wall to electrical ground by way of connection to one or more ground bond pads on the substrate.

2. The semiconductor package of claim 1 , further comprising a lid comprising the wall and a cover portion integrally formed with the wall, and an integrated device die mounted to the package substrate within a cavity defined by the semiconductor package.

3. The semiconductor package of claim 1 , wherein the integrated device die comprises a gallium arsenide (GaAs) die, a gallium nitride (GaN) die, or a Group III-V semiconductor die.

4. The semiconductor device of claim 1 , wherein the second adhesive layer is a closed annulus surrounding the outer perimeter of the first adhesive layer.

5. The semiconductor package of claim 1 , wherein the first adhesive layer is denser than the second adhesive layer.

6. The semiconductor package of claim 1 , further comprising a solder mask dam positioned on the substrate proximate the wall,
wherein a portion of the first or second adhesive layer is adhered to the solder mask dam,
wherein the solder mask dam comprises a first portion adjacent a second portion, the first and second portions separated by a gap,
wherein the gap exposes a portion of the substrate, and
wherein the first or second adhesive layer is electrically grounded via connection to one or more ground bond pads comprising conductive traces of the substrate exposed in the gap.

7. The semiconductor package of claim 1 , wherein the first adhesive layer and the second adhesive layer form a seal that seals the wall to the substrate, wherein the seal is configured to withstand standard temperature humidity bias (THB) testing at 85 degrees Celsius and 85 percent humidity in the range of 1000 hours to 3000 hours.

8. The semiconductor package of claim 1 , wherein the material of the second adhesive layer is more effective at inhibiting moisture from permeating into the package from the outside environs than the first adhesive layer.

9. A semiconductor package comprising:
a substrate;
a wall attached to the substrate;
a first epoxy layer disposed between a bottom surface of the wall and a top surface of the substrate; and
a second epoxy layer disposed around an outer perimeter of the first epoxy layer, the second epoxy layer disposed adjacent and contacting the wall,
wherein the first epoxy layer comprises an epoxy comprising a material different from the second epoxy layer, the first epoxy layer comprising a conductive filler.

10. The semiconductor package of claim 9 , further comprising a lid comprising the wall and a cover portion integrally formed with the wall, and an integrated device die mounted to the package substrate within a cavity defined by the semiconductor package,
wherein the integrated device die comprises a gallium arsenide (GaAs) die, a gallium nitride (GaN) die, or a Group semiconductor die.

11. The semiconductor package of claim 9 , wherein at least a portion of the second epoxy layer is disposed between the bottom surface of the wall and the top surface of the substrate.

12. The semiconductor package of claim 9 , wherein the first epoxy layer comprises a silver or copper filled epoxy and the second epoxy layer comprises a non-conductive epoxy.

13. The semiconductor package of claim 9 , wherein the second epoxy layer contacts the first epoxy layer about the outer perimeter.

14. The semiconductor package of claim 9 , wherein the second epoxy layer is a closed annulus surrounding the outer perimeter of the first epoxy layer, and wherein the second epoxy layer contacts the first epoxy layer between a bottom surface of the wall and a top surface of the substrate.

15. The semiconductor package of claim 9 , wherein the first or second epoxy layer connects the wall to electrical ground by way of connection to one or more ground bond pads on the substrate.

16. The semiconductor package of claim 9 , wherein the second epoxy layer contacts the first epoxy layer between a bottom surface of the wall and a top surface of the substrate.

17. The semiconductor package of claim 9 , wherein the first epoxy layer and the second epoxy layer form a seal that seals the wall to the substrate, wherein the seal is configured to withstand standard temperature humidity bias (THB) testing at 85 degrees Celsius and 85 percent humidity in the range of 1000 hours to 3000 hours.

18. A semiconductor package comprising:
a substrate;
a wall attached to the substrate;
an epoxy layer disposed between a bottom surface of the wall and a top surface of the substrate, the epoxy comprising a conductive filler; and
a solder layer disposed around an outer perimeter of the epoxy layer, the solder layer disposed adjacent and contacting the wall,
a solder mask dam positioned on the substrate proximate the wall,
wherein the epoxy or solder layer connects the wall to electrical ground by way of connection to one or more ground bond pads on the substrate,
wherein a portion of the epoxy and solder layer is adhered to the solder mask dam, wherein the solder mask dam comprises a first portion adjacent a second portion, the first and second portions separated by a gap,
wherein the gap exposes a portion of the substrate, and
wherein the epoxy or solder layer is electrically grounded via connection to one or more ground bond pads comprising conductive traces of the substrate exposed in the gap.

19. The semiconductor package of claim 18 , further comprising a lid comprising the wall and a cover portion integrally formed with the wall, and an integrated device die mounted to the package substrate within a cavity defined by the semiconductor package,
wherein the integrated device die comprises a gallium arsenide (GaAs) die, a gallium nitride (GaN) die, or a Group semiconductor die.

Assignees

• Analog Devices Inc

Inventors

• Bolognia David
• Zhu Jingwen

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W76/60 Primary

  Seals · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title