FinFETs with nitride liners and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9870956-B2
Application number	US-201615213524-A
Country	US
Kind code	B2
Filing date	Jul 19, 2016
Priority date	Jun 21, 2013
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.

First claim

What is claimed is:

1. A method comprising:
etching a semiconductor substrate to form a first recess;
forming a nitride liner lining a bottom and a sidewall of the first recess; forming an oxide region in the first recess and over the nitride liner;
forming a nitride region to cover the oxide region, wherein the nitride region, the nitride liner, and the oxide region in combination form a Shallow Trench Isolation (STI) region, wherein before forming the nitride region, the oxide region is recessed to form a recessed oxide region, and the nitride region is formed over the recessed oxide region; recessing a semiconductor fin to form a second recess between opposing portions of the nitride liner;
removing a top portion of the nitride region and a top portion of the nitride liner and
performing an epitaxy to form a semiconductor re-growth region in the second recess, wherein the semiconductor re-growth region on a side and contacting the nitride liner is higher than the STI region.

2. The method of claim 1 further comprising:
forming a gate dielectric on a top surface and sidewalls of the semiconductor re-growth region, wherein the gate dielectric is in contact with a top surface of a remaining bottom portion of the nitride region; and
forming a gate electrode over the gate dielectric, wherein the gate dielectric, the gate electrode, the semiconductor re-growth region, and the semiconductor fin comprise a Fin Field-Effect Transistor (FinFET).

3. The method of claim 1 further comprising:
forming a pad oxide layer and a hard mask layer over the semiconductor substrate;
patterning the pad oxide layer and the hard mask layer to form a patterned pad oxide layer and a patterned hard mask layer, respectively;
performing the step of etching the semiconductor substrate using the patterned hard mask layer as a mask; and
performing the step of forming the nitride liner, wherein the nitride liner extends on sidewalls and a top surface of remaining portions of the hard mask layer.

4. The method of claim 1 further comprising before forming the nitride region, annealing the oxide region.

5. The method of claim 4 , wherein the annealing comprises at least one of:
a temperature between about 800° C. and about 1050° C. for a duration of time between about 1 minute and about 20 minutes; or
a temperature between about 200° C. and about 700° C. for a duration of time between about 30 minutes and about 120 minutes with a process gas comprising oxygen, hydrogen, or nitrogen.

6. The method of claim 1 further comprising, after forming the nitride region, performing a planarization to remove portions of the nitride region and the nitride liner over the semiconductor fin to expose the semiconductor fin.

7. The method of claim 6 , wherein the semiconductor re-growth region comprises silicon germanium with an atomic percentage of germanium greater than 0% and less than or equal to 100%.

8. The method of claim 6 , wherein the removing the top portion of the nitride region is performed after the epitaxy.

9. A method comprising:
etching a semiconductor substrate to form a first recess;
forming a first nitride region lining a bottom and a sidewall of the first recess; forming an oxide region in the first recess and over the first nitride region; forming a second nitride region to cover the oxide region, wherein the second nitride region, the first nitride region, and the oxide region in combination form a Shallow Trench Isolation (STI) region, wherein before forming the second nitride region, the oxide region is recessed to form a recessed oxide region, and the second nitride region is formed over the recessed oxide region;
recessing a semiconductor fin to form a second recess between opposing portions of the first nitride region;
removing a top portion of the second nitride region and a top portion of the first nitride region and
performing an epitaxy to form a semiconductor re-growth region in the second recess, wherein the semiconductor re-growth region on a side and contacting the first nitride region has a top surface that is higher than a top surface of the STI region.

10. The method of claim 9 further comprising:
forming a gate dielectric on a top surface and sidewalls of the semiconductor re-growth region, wherein the gate dielectric is in contact with a top surface of a remaining bottom portion of the second nitride region; and
forming a gate electrode over the gate dielectric, wherein the gate dielectric, the gate electrode, the semiconductor re-growth region, and the semiconductor fin are comprised in a Fin Field-Effect Transistor (FinFET).

11. The method of claim 9 further comprising:
forming a hard mask layer over the semiconductor substrate;
patterning the hard mask layer to form a patterned hard mask;
performing the step of etching the semiconductor substrate using the patterned hard mask as an etching mask; and
performing the step of forming the first nitride region, wherein the first nitride region extends on sidewalls and a top surface of remaining portions of the hard mask layer.

12. The method of claim 9 further comprising before forming the second nitride region, annealing the oxide region.

13. The method of claim 12 , wherein the annealing comprises at least one of:
a temperature between about 800° C. and about 1050° C. for a duration of time between about 1 minute and about 20 minutes; or
a temperature between about 200° C. and about 700° C. for a duration of time between about 30 minutes and about 120 minutes with a process gas comprising oxygen, hydrogen, or nitrogen.

14. The method of claim 9 further comprising, after forming the second nitride region, performing a planarization to remove portions of the second nitride region and the first nitride region over the semiconductor fin to expose the semiconductor fin.

15. The method of claim 14 , wherein the removing the top portion of the second nitride region is performed after the epitaxy.

16. A method comprising:
forming a first recess in a semiconductor substrate;
lining a bottom surface and a sidewall surface of the first recess with a first nitride region;
depositing an oxide region in the first recess and over the first nitride region; forming a second nitride region over the oxide region, wherein the second nitride region, the first nitride region, and the oxide region in combination form a Shallow Trench Isolation (STI) region, wherein before forming the second nitride region, the oxide region is recessed to form a recessed oxide region, and the second nitride region is formed over the recessed oxide region;
recessing an upper-most portion of the semiconductor substrate to form a second recess between opposing portions of the first nitride region; and
epitaxially forming a semiconductor fin in the second recess, wherein the semiconductor fin is higher than an upper-most surface of the STI region.

17. The method of claim 16 further comprising removing a top portion of the second nitride region and a top portion of the first nitride region.

18. The method of claim 16 further comprising:
forming a gate dielectric on a top surface and sidewalls of the semiconductor fin, wherein the gate dielectric is in contact with a top surface of a bottom portion of the second nitride region; and
forming a gate electrode over the gate dielectric, wherein the gate dielectric, the gate electrode, and the semiconductor fin comprise a Fin Field-Effect Transistor (FinFET).

19. The method of claim 16 , wherein the semiconductor fin comprises silicon germanium

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Neng-Kuo
• Huang Gin-Chen
• Jiang Ching-Hong
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/823431

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic