Low power digital driving of active matrix displays

Patent metadata

Field	Value
Publication number	US-9870757-B2
Application number	US-201314647250-A
Country	US
Kind code	B2
Filing date	Nov 25, 2013
Priority date	Nov 26, 2012
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Digital driving circuitry for driving an active matrix display comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, each pixel comprising a light emitting element, comprises a current driver for each of the plurality of columns for driving a predetermined current through the corresponding column, the predetermined current being proportional to the number of pixels that are ON in that column. The digital driving circuitry further comprises digital select line driving circuitry for sequentially selecting the plurality of rows, and digital data line driving circuitry for writing digital image codes to the pixels in a selected row, synchronized with the digital select line driving circuitry.

First claim

The invention claimed is:

1. Digital driving circuitry for driving an active matrix display, the display comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, each pixel comprising a light emitting element, wherein the driving circuitry comprises:
current driver circuitry for each of the plurality of columns and configured to drive a predetermined current through the corresponding column, the predetermined current being proportional to the number of pixels that are ON in that column,
a first line with a first resistive path and a second line with a second resistive path between which the predetermined current is configured to be driven through each column, wherein the resistance of the first resistive path is substantially equal to the resistance of the second resistive path over a length of the first and second lines for all light emitting elements in each column,
digital select line driving circuitry configured to sequentially select the plurality of rows, and
digital data line driving circuitry configured to write digital image codes to the pixels in a selected row, synchronized with the digital select line driving; circuitry;
wherein each current driver circuitry contains a counter for storing a natural number equal to the number of light emitting elements that are ON in the corresponding column at a given moment in time, wherein the counter is synchronized with the select line driving circuitry and responsive to changes in the digital data line driving circuitry.

2. The digital driving circuitry according to claim 1 , wherein the display comprises a backplane, and wherein the current driver circuitry is external to the display backplane.

3. The digital driving circuitry according to claim 1 , wherein the current driver circuitry comprises monocrystalline semiconductor-based circuits.

4. The digital driving circuitry according to claim 1 , wherein the counter is an up down counter.

5. The digital driving circuitry according to claim 1 , further comprising a backplane comprising pixel driving circuitry connectable to the plurality of light emitting elements of the display, wherein each pixel driving circuitry comprises means for compensating differences in voltage drop between different pixels in a column, the voltage drop being determined over a series connection of the light emitting element and the pixel driving circuitry.

6. The digital driving circuitry according to claim 5 , wherein the means for compensating further comprises means for applying digital compensation.

7. The digital driving circuitry according to claim 5 , wherein the means for compensating further comprises means for applying analog compensation.

8. A method for digital driving of an active matrix display, the display comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, the method comprising:
sequentially selecting each of the plurality of rows using digital select line driving circuitry;
writing digital image data to the pixels in a selected row using digital data line driving circuitry; and
driving a predetermined current through each column, the predetermined current for a given column being proportional to the number of pixels that are ON in that column, wherein driving the predetermined current through each column comprises driving the predetermined current between a current source comprising a first resistive path and a current sink comprising a second resistive path, and wherein the resistances of the first and second resistive paths are substantially equal;
wherein, for each column, storing a natural number equal to the number of pixels that are ON in that column at a given moment in time, the number being synchronized with the select line driving circuitry and being updated according to changes in the data line driving circuitry.

9. The method according to claim 8 , further comprising performing a calibration step, thereby determining a preferred voltage drop for each column and imposing that preferred voltage drop for each of the pixels in the corresponding column.

10. The method according to claim 9 , wherein determining the preferred voltage drop comprises determining the voltage drop as a voltage difference over a series connection of the pixel and a pixel driving circuit coupled to the pixel.

Assignees

• Imec Vzw
• Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno

Inventors

• Genoe Jan

Classifications

• G09G2320/0693

  Calibration of display systems · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G3/3283 Primary

  in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title