Display device

Patent metadata

Field	Value
Publication number	US-9870749-B2
Application number	US-201514833336-A
Country	US
Kind code	B2
Filing date	Aug 24, 2015
Priority date	Sep 17, 2014
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A display device includes a pixel array having a plurality of pixels arranged in a matrix form based on a crossing structure of data lines and gate lines, a data driver having a plurality of output channels and configured to output a data voltage, a multiplexer configured to distribute the data voltage output from the data driver to the data lines in response to first and second control signals, and a gate driver configured to output a gate pulse synchronized with the data voltage in a non-sequential manner. The first and second control signals are in antiphase, and a switching cycle of the first and second control signals is one horizontal period or two horizontal periods.

First claim

What is claimed is:

1. A display device comprising:
a pixel array including a plurality of subpixels arranged in a matrix form based on a crossing structure of data lines and gate lines, the subpixels including at least subpixels of a first color and subpixels of a second color different from the first color;
a data driver including a plurality of output channels to output data voltages, respectively;
a multiplexer connected between the pixel array and the data driver, and configured to distribute the data voltages output from the data driver to the data lines, respectively, in response to first and second control signals from a controller; and
a gate driver connected to the pixel array, and configured to output gate pulse synchronized with the data voltages to the gate lines in a non-sequential manner,
wherein the first and second control signals are in antiphase with each other, and a switching cycle of the first and second control signals is one horizontal period or two horizontal periods,
wherein a data switching cycle of the data voltages supplied to the pixel array is N horizontal periods, where N is a positive even number greater than or equal to 4, and
wherein the data driver is configured to provide data voltages of the first color successively to N subpixels of the first color via one of the output channels within N/2 successive horizontal periods.

2. The display device of claim 1 , wherein the multiplexer includes:
a first switch connected between a first output channel of the data driver and a first data line and configured to supply a data voltage from the first output channel to the first data line in response to the first control signal;
a second switch connected between the first output channel and a third data line and configured to supply the data voltage from the first output channel to the third data line response to the second control signal;
a third switch connected between a second output channel of the data driver and a second data line and configured to supply a data voltage from the second output channel to the second data line in response to the first control signal; and
a fourth switch connected between the second output channel and a fourth data line and configured to supply the data voltage from the second output channel to the fourth data line in response to the second control signal,
wherein the switching cycle of the first and second control signals is one horizontal period,
wherein the gate pulse is supplied to the gate lines in order of a first gate line, a third gate line, a second gate line, and a fourth gate line, and
wherein the data voltages of the first color are configured to be successively supplied to four subpixels of the first color via the one of the output channels during two successive horizontal periods, and then data voltages of the second color are configured to be successively supplied to four subpixels of the second color via the one of the output channels during next two successive horizontal periods.

3. The display device of claim 1 , wherein the multiplexer includes:
a first switch connected between a first output channel of the data driver and a first data line and configured to supply a data voltage from the first output channel to the first data line in response to the first control signal;
a second switch connected between the first output channel and a third data line and configured to supply the data voltage from the first output channel to the third data line in response to the second control signal;
a third switch connected between a second output channel of the data driver and a second data line and configured to supply a data voltage from the second output channel to the second data line in response to the first control signal; and
a fourth switch connected between the second output channel and a fourth data line and configured to supply the data voltage from the second output channel to the fourth data line in response to the second control signal,
wherein the switching cycle of the first and second control signals is two horizontal periods,
wherein the gate pulse is supplied to the gate lines in order of a first gate line, a third gate line, a second gate line, and a fourth gate line, and
wherein the data voltages of the first color are configured to be successively supplied to four subpixels of the first color via the one of the output channels during two successive horizontal periods, and then data voltages of the second color are configured to be successively supplied to four subpixels of the second color via the one of the output channels during next two successive horizontal periods.

4. The display device of claim 1 , wherein the multiplexer includes:
a first switch connected between a first output channel of the data driver and a first data line and configured to supply a data voltage from the first output channel to the first data line in response to the first control signal;
a second switch connected between the first output channel and a third data line and configured to supply the data voltage from the first output channel to the third data line in response to the second control signal;
a third switch connected between a second output channel of the data driver and a second data line and configured to supply a data voltage from the second output channel to the second data line in response to the first control signal; and
a fourth switch connected between the second output channel and a fourth data line and configured to supply the data voltage from the second output channel to the fourth data line in response to the second control signal,
wherein the switching cycle of the first and second control signals is one horizontal period,
wherein the gate pulse is supplied to the gate lines in order of a first gate line, a third gate line, a fifth gate line, a second gate line, a fourth gate line, and a sixth gate line, and
wherein the data voltages of the first color are configured to be successively supplied to six subpixels of the first color via the one of the output channels during three successive horizontal periods, and then data voltages of the second color are configured to be successively supplied to six subpixels of the second color via the one of the output channels during next three successive horizontal periods.

5. The display device of claim 1 , wherein the multiplexer includes:
a first switch connected between a first output channel of the data driver and a first data line and configured to supply a data voltage from the first output channel to the first data line in response to the first control signal;
a second switch connected between the first output channel and a third data line and configured to supply the data voltage from the first output channel to the third data line in response to the second control signal;
a third switch connected between a second output channel of the data driver and a second data line and configured to supply a data voltage from the second output channel to the second data line in response to the first control signal; and
a fourth switch connected between the second output channel and a fourth data line and configured to supply the data voltage from the second output channel to the fourth data line in response to the second control signal,
wherein the switching cycle of the first and second control signals is one horizontal period,
wherein the gate pulse is supplied to the gate lines in order of a first gate line, a third gate line, a fifth gate line, a second gate line, a fourth gate line, a sixth gate line, a seventh gate line, and a ninth gate line, and
wherein the data voltages of the first color are configured to be successively supplied to eight subpixels of the first color via the one of the output channels during four successive horizontal periods, and then

Assignees

• Lg Display Co Ltd

Inventors

• Yoo Seungjin
• Sang Wookyu
• Yoo Ooksang

Classifications

• G09G2310/0224

  Details of interlacing · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title