Interleaved all-level programming of non-volatile memory

Patent metadata

Field	Value
Publication number	US-9870169-B2
Application number	US-201514846102-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Sep 4, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.

First claim

What is claimed is:

1. A method for programming a non-volatile memory device having a plurality of word lines each operatively coupled to a plurality of multi-level storage cells, the method comprising:
programming word line n to an intermediate voltage level;
programming word line n+1 to an intermediate voltage level;
programming word line n to its target voltage level;
programming word line n+2 to an intermediate voltage level;
programming word line n+1 to its target voltage level;
programming word line n+2 to its target voltage level; and
suppressing reads to word line n, word line n+1, and word line n+2, until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level.

2. The method of claim 1 wherein the programming of a given word line is carried out using a sawtooth pattern of programming voltage.

3. The method of claim 1 , further comprising at least one of:
receiving data to be written to the non-volatile memory from a host; and
buffering the data in a temporary storage.

4. The method of claim 3 wherein the temporary storage is a volatile memory, the method further comprising:
moving the data from the volatile memory to the non-volatile memory using the programming of word lines n, n+1, and n+2.

5. The method of claim 3 , further comprising:
writing the data from the temporary storage to a phase change memory with switch (PCMS) using a PCMS controller.

6. The method of claim 5 wherein in response to a sufficient amount of the data being stored in the PCMS, the method further comprises:
moving the data from the PCMS to the non-volatile memory using the programming of word lines n, n+1, and n+2.

7. A storage controller device, comprising:
one or more memory controllers configured to facilitate movement of staged data from a staging buffer to a non-volatile memory, the non-volatile memory having a plurality of word lines each operatively coupled to a plurality of storage cells, at least one of the one or more controllers configured to
program word line n to an intermediate voltage level,
program word line n+1 to an intermediate voltage level,
program word line n to its target voltage level,
program word line n+2 to an intermediate voltage level,
program word line n+1 to its target voltage level,
program word line n+2 to its target voltage level, and
suppress reads to word line n, word line n+1, and word line n+2 until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level.

8. The device of claim 7 wherein the one or more controllers includes at least one of:
a buffer controller configured to facilitate the writing of data to the staging buffer; and
a controller configured to facilitate the writing of data to the non-volatile memory.

9. The device of claim 7 , further comprising:
a temporary buffer configured to store data before that data is transferred to the staging buffer.

10. The device of claim 7 further comprising the staging buffer and the non-volatile memory, the staging buffer configured to stage data received from a host system, and the non-volatile memory configured to store data staged in the staging buffer.

11. The device of claim 7 wherein the non-volatile memory comprises NAND flash memory, and the one or more controllers includes a NAND controller configured to interface with the NAND flash memory.

12. The device of claim 7 wherein the staging buffer comprises a phase change memory with switch (PCMS), and the one or more controllers includes a PCMS controller configured to interface with the PCMS.

13. The device of claim 7 wherein the staging buffer is a volatile memory.

14. The device of claim 7 wherein each word line is partitioned into a plurality of pages, such that programming each of word lines n, n+1, and n+2 provides six or more pages of data.

15. The device of claim 7 wherein each word line is partitioned into four pages: a first page for the first of 4-bits per cell in a given word line, a second page for the second of the 4-bits per cell in the given word line, a third page for the third of the 4-bits per cell in the given word line, and a fourth page for the fourth of the 4-bits per cell in the given word line.

16. The device of claim 7 wherein each word line is partitioned into four pages, such that programming each of word lines n, n+1, and n+2 provides twelve pages of data including page 0 through page 11 , and wherein at least one of the one or more controllers is configured to:
program word line n to an intermediate voltage level by coarse programming pages 0 and 1 ;
program word line n+1 to an intermediate voltage level by coarse programming pages 2 and 3 ;
program word line n to its target voltage level by fine programming pages 4 and 5 , along with pages 0 and 1 ;
program word line n+2 to an intermediate voltage level by coarse programming pages 6 and 7 ;
program word line n+1 to its target voltage level by fine programming pages 8 and 9 , along with pages 2 and 3 ; and
program word line n+2 to its target voltage level by fine programming pages 10 and 11 , along with pages 6 and 7 .

17. The device of claim 7 , further comprising a host interface configured to receive data for storage, wherein the device is part of a computing system.

18. The device of claim 7 wherein at least one of the one or more controllers is configured to suppress reads by holding reads or delaying issuance of reads.

19. The device of claim 18 wherein the held reads are buffered.

20. A solid-state storage system, comprising:
a host interface configured to receive data for storage;
a phase change memory with switch (PCMS) configured to stage data received by the host interface;
a PCMS controller configured to facilitate the writing of data to the PCMS;
NAND flash memory configured to store data staged in the PCMS and having a plurality of word lines each operatively coupled to a plurality of storage cells;
a NAND controller configured to facilitate the writing of data to the NAND flash memory;
a processor configured to facilitate movement of staged data from the PCMS to the NAND flash memory, wherein processor is configured to
program word line n to an intermediate voltage level,
program word line n+1 to an intermediate voltage level,
program word line n to its target voltage level,
program word line n+2 to an intermediate voltage level,
program word line n+1 to its target voltage level,
program word line n+2 to its target voltage level, and
suppress reads to word line n, word line n+1, and word line n+2 until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level.

21. The system of claim 20 further comprising:
a temporary buffer configured to store data from the host interface before that data is transferred to the PCMS.

22. The system of claim 20 wherein each word line is partitioned into four pages: a first page for the first of 4-bits per cell in a given word line, a second page for the second of the 4-bits per cell in the given word line, a third page for the third of the 4-bits per cell in the given word line, and a fourth page for the fourth of the 4-bits per cell in the given word line.

23. The system of claim 20 wherein each word line is partitioned into four pages, such that programming each of word lines n, n+1, and n+2 provides twelve pages of data including page 0 through page 11 , and wherein the

Assignees

• Intel Corp

Inventors

• Ramalingam Anand S
• Juenemann Dale J
• Kalavade Pranav

Classifications

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G06F2212/261

  Storage comprising a plurality of storage devices · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title