Digitally phase locked low dropout regulator apparatus and system using ring oscillators

Patent metadata

Field	Value
Publication number	US-9870012-B2
Application number	US-201213976223-A
Country	US
Kind code	B2
Filing date	Sep 25, 2012
Priority date	Sep 25, 2012
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.

First claim

We claim:

1. An apparatus comprising:
a first oscillator to generate a first clock signal;
a second oscillator to generate a second clock signal;
a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and
an output stage comprising a p-type transistor, coupled to a load, to generate a power supply for the load according to the phase difference, wherein a gate terminal of the p-type transistor is to receive the phase difference as a digital pulse,
wherein the first and second oscillators include equal number of delay stages.

2. The apparatus of claim 1 , wherein the p-type transistor comprises:
a first terminal which is coupled to an input power supply; and
a second terminal to provide the power supply to the load.

3. The apparatus of claim 1 , wherein the first oscillator is controllable by a first reference generated by a reference generator.

4. The apparatus of claim 1 , wherein the second oscillator is controllable by a second reference which corresponds to the power supply generated by the output stage for the load.

5. The apparatus of claim 1 , wherein the first and second oscillators are voltage controlled oscillators.

6. The apparatus of claim 1 , wherein the phase frequency detector comprises a Johnson counter.

7. The apparatus of claim 1 , wherein the load is a portion of a processor.

8. An apparatus comprising:
a first oscillator to generate a first clock signal;
a second oscillator to generate a second clock signal; and
an N-bit Johnson Counter to generate N number of phases of the first and second clock signals, the N number of phases to directly or indirectly regulate power supply for one or more loads, where N is an integer, and wherein the N-bit Johnson Counter comprises an embedded output stage which is to provide the regulated power supply.

9. The apparatus of claim 8 further comprises N output drivers are embedded in the N-bit Johnson Counter.

10. The apparatus of claim 9 , wherein each of the N output drivers is operable to generate an output power supply for the one or more loads from an input power supply.

11. The apparatus of claim 9 , wherein the N output drivers generate N reference voltages for a common node having the output power supply, the output power supply for controlling the second oscillator.

12. The apparatus of claim 8 , wherein the first oscillator is controllable by a first reference, wherein the second oscillator is controllable by a second reference, and wherein the first and the second references are generated from difference sources.

13. The apparatus of claim 12 , wherein the first reference is generated by a reference generator, and wherein the second reference is generated according to a phase difference between the first and second clock signals.

14. The apparatus of claim 8 , wherein the first and second oscillators comprise delay stages having current starved inverters.

15. The apparatus of claim 8 , wherein the first and second oscillators are identical.

16. A system comprising:
a memory;
a processor, coupled to the memory, the processor including multiple processing cores, each processing core having one or more low dropout regulators (LDOs), wherein the one or more LDOs comprise:
a first oscillator to generate a first clock signal;
a second oscillator to generate a second clock signal;
a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and
an output stage comprising a p-type transistor, coupled to a load, to generate a power supply for the load according to the phase difference, wherein a gate terminal of the p-type transistor is to receive the phase difference as a digital pulse; and

a wireless interface to allow the processor to communicate with other devices.

17. The system of claim 16 further comprises a display.

18. An apparatus comprising:
a phase detector to detect phase difference between first and second clock signals generated from respective first and second oscillators, wherein the first and second oscillators include equal number of delay stages; and
an output stage, coupled to a load, to generate a power supply for the load according to the phase difference as a digital pulse.

19. The apparatus of claim 18 , wherein the phase detector to generate a pulse modulated signal to represent the phase difference.

20. The apparatus of claim 18 , wherein the first and second oscillators have identical floor plans.

21. The apparatus of claim 18 , wherein the first and second oscillators are voltage controlled oscillators, each including:
a first chain of delay stages;
a second chain of delay stages; and
a multiplexer which is operable to select one of the first or second chain of delay stages according to a select signal, wherein the multiplexer and the first and second chain of delay stages are coupled together to form a loop.

22. The apparatus of claim 21 , wherein each of the delay stages in the first and second chains of delay stages comprises current starved inverters.

23. An apparatus comprising:
an output stage, to be coupled to a load, to generate a power supply for the load according to a phase difference between first and second clock signals generated from respective first and second oscillators, wherein the output stage comprises a voltage level-shifter coupled to a control logic which is to operate at a supply lower than an input power supply, and wherein the input power supply is coupled to p-type transistor of the output stage.

24. The apparatus of claim 23 , wherein the the p-type transistor is coupled to the voltage level-shifter.

25. The apparatus of claim 23 , wherein the output stage further comprises an overflow protection logic to propagate a first control when the first control and a second control are unequal, and to propagate the second control when the first control and the second control are equal to each other.

26. The apparatus of claim 23 , wherein the first oscillator is controllable by a first reference generated by a reference generator, and wherein the second oscillator is controllable by a second reference which corresponds to the power supply generated by the output stage for the load.

27. The apparatus of claim 23 , wherein the first and second oscillators are voltage controlled oscillators.

Assignees

• Intel Corp

Inventors

• Raychowdhury Arijit
• Somasekhar Dinesh
• Tschanz James W
• De Vivek K

Classifications

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title