Lithography process

US9869939B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9869939-B2
Application numberUS-201514733719-A
CountryUS
Kind codeB2
Filing dateJun 8, 2015
Priority dateMar 15, 2013
Publication dateJan 16, 2018
Grant dateJan 16, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second set of registration marks is formed on the substrate using the second mask and a second exposure tool. A second set of overlay errors is determined. A set of tool-induced overlay errors is generated from the first and second sets of overlay errors and used in fabricating a third mask. The third mask can then be used in the lithography process to accommodate the overlay errors caused by different exposure tools, different masks, and different mask writers.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: providing a substrate having a set of baseline registration marks; forming a first set of registration marks, defined by a first mask, on the substrate; determining a first set of overlay errors of the first set of registration marks with respect to the set of baseline registration marks; forming a second set of registration marks, defined by a second mask, on the substrate; determining a second set of overlay errors of the second set of registration marks with respect to the set of baseline registration marks; generating a set of tool-induced overlay errors from the first set of overlay errors and the second set of overlay errors; and fabricating a device by using a third mask fabricated using the set of tool-induced overlay errors. 2. The method of claim 1 , wherein the first mask is fabricated by a first mask writer with a first grid table, and wherein the second mask is fabricated by a second mask writer with a second grid table. 3. The method of claim 1 , further comprising prior to forming the second set of registration marks on the substrate, removing the first set of registration marks from the substrate. 4. The method of claim 2 , wherein the first mask writer and the second mask writer are a same mask writer. 5. The method of claim 1 , wherein the forming the first set of registration marks further includes forming the first set of registration marks using the first mask and a first exposure tool, and wherein the forming the second set of registration marks further includes forming the second set of registration marks using the second mask and a second exposure tool. 6. The method of claim 1 , wherein the first set of registration marks is formed on a first resist layer on the substrate. 7. The method of claim 6 , further comprising: after determining the first set of overlay errors, removing the first resist layer; and forming a second resist layer on the substrate. 8. The method of claim 7 , wherein the second set of registration marks is formed on the second resist layer. 9. The method of claim 2 , wherein the set of tool-induced overlay errors is generated by subtracting the second set of overlay errors from the first set of overlay errors and the third mask is fabricated by the first mask writer with an adjusted first grid table obtained by subtracting the set of tool-induced overlay errors from the first grid table. 10. The method of claim 9 , wherein the third mask is used on the first exposure tool to expose a layer which is needed to align a layer exposed by the second exposure tool. 11. The method of claim 2 , wherein the set of tool-induced overlay errors is generated by subtracting the first set of overlay errors from the second set of overlay errors and the third mask is fabricated by the second mask writer with an adjusted second grid table obtained by subtracting the set of tool-induced overlay errors from the second grid table. 12. The method of claim 11 , wherein the third mask is used on the second exposure tool to expose a layer which is needed to align a layer exposed by the first exposure tool. 13. A method comprising: providing a first mask fabricated by a first mask writer with a first grid table for exposing a first layer on the first exposure tool; providing a second mask fabricated by a second mask writer with a second grid table for exposing a second layer on the second exposure tool; receiving a substrate with a set of baseline registration marks; forming a first resist layer on the substrate; forming a first set of registration marks on the first resist layer using the first mask and the first exposure tool; measuring a first set of overlay errors of the first set of registration marks with respect to the set of baseline registration marks; after measuring the first set of overlay errors, removing the first resist layer and forming a second resist layer on the substrate; forming a second set of registration marks on the second resist layer using the second mask and the second exposure tool; measuring a second set of overlay errors of the second set of registration marks with respect to the set of baseline registration marks; generating a set of tool-induced overlay errors from the first set of overlay errors and the second set of overlay errors; and fabricating a device using a third mask, the third mask fabricated using the set of tool-induced overlay errors. 14. The method of claim 13 , wherein the fabricating the device further includes fabricating the device using the third mask on the first exposure tool and the second mask on the second exposure tool. 15. The method of claim 13 , wherein the fabricating the device further includes fabricating the device using the third mask on the first exposure tool and a new second mask, which is fabricated by the second mask writer with the second grid table, on the second exposure tool. 16. The method of claim 13 , wherein the fabricating the device further includes fabricating the device using the first mask on the first exposure tool and the third mask on the second exposure tool. 17. The method of claim 13 , wherein the fabricating the device further includes fabricating the device using a new first mask, which is fabricated by the first mask writer with the first grid table, on the first exposure tool and the third mask on the second exposure tool. 18. A method comprising: receiving a first set of overlay errors from a first mask used on a first exposure tool, the first set of overlay errors based on a first set of registration marks measured with respect to a set of baseline registration marks; receiving a second set of overlay errors from a second mask used on a second exposure tool, the second set of overlay errors based on a second set of registration marks measured with respect to the set of baseline registration marks; determining a set of tool-induced overlay errors from the first set of overlay errors and the second set of overlay errors; fabricating a third mask based on the set of tool-induced overlay errors; and fabricating a device by using the third mask. 19. The method of claim 18 , wherein the first mask is fabricated by using a first grid table and the third mask is fabricated by using an adjusted first grid table obtained by subtracting the set of tool-induced overlay errors from the first grid table, wherein the set of tool-induced overlay errors is obtained by subtracting the second set of overlay errors from the first set of overlay errors, if the third mask is to be used on the first exposure tool for patterning a first layer, which is to be aligned to a second layer exposed on the second exposure tool. 20. The method of claim 18 , wherein the second mask is fabricated by using a second grid table and the third mask is fabricated by using an adjusted second grid table obtained by subtracting the set of tool-induced overlay errors from the second grid table, wherein the set of tool-induced overlay errors is obtained by subtracting the first set of overlay errors from the second set of overlay errors, if the third mask is to be used for patterning a second layer, which is to be aligned to a first layer exposed on the first exposure tool, on the second exposure tool.

Assignees

Inventors

Classifications

  • Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

  • Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

  • Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

  • Exposure; Apparatus therefor (photographic printing apparatus for making copies G03B27/00) · CPC title

  • Alignment or registration features, e.g. alignment marks on the mask substrates · CPC title

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What does patent US9869939B2 cover?
A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification G03F7/70633. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 16 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).