Array substrate and method of manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-9869902-B2
Application number	US-201514778763-A
Country	US
Kind code	B2
Filing date	May 21, 2015
Priority date	Sep 26, 2014
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

An array substrate, a method of manufacturing the array substrate, and a display device are disclosed, for eliminating white Mura defects generated during the Cell process. The method comprises steps of: forming a display area and a non-display area on a substrate, a circuit bonding area being arranged within the non-display area; forming an alignment film within the display area through a patterning process; forming, through a patterning process, a transparent protection layer at least in a portion of the non-display area other than the circuit bonding area; and forming, through a rubbing-imprinting process, a plurality of lines having the same orientation on a surface of the alignment film, for an ordered arrangement of liquid crystal molecules, wherein a surface height of the transparent protection layer is lower than or equal to a surface height of the alignment film.

First claim

What is claimed is:

1. A method of manufacturing an array substrate, comprising steps of:
forming a display area and a non-display area on a substrate, a circuit bonding area being arranged within the non-display area;
forming an alignment film in the display area through a patterning process;
forming, through a patterning process, a transparent protection layer at least in a portion of the non-display area other than the circuit bonding area; and
forming, through a rubbing-imprinting process, a plurality of lines having the same orientation on a surface of the alignment film, for an ordered arrangement of liquid crystal molecules,
wherein a surface height of the transparent protection layer is lower than or equal to a surface height of the alignment film; and
wherein the step of forming the transparent protection layer comprises:
coating a first resin layer on a surface of the substrate on which the alignment film has been formed, such that the alignment film is located between the substrate and the first resin layer;
forming a photoresist layer on a surface of the first resin layer;
forming, through a single masking and exposing process and a single development process, a first full coverage area of the photoresist layer and a first full removal area of the photoresist layer, the first full coverage area of the photoresist layer corresponding to the transparent protection layer to be formed and the first full removal area of the photoresist layer corresponding to the circuit bonding area and a pattern of the alignment film;
etching a portion of the first resin layer corresponding to the first removal area of the photoresist layer; and
peeling off the photoresist in the first full coverage area of the photoresist layer, so that a remaining portion of the first resin layer forms the transparent protection layer.

2. The method according to claim 1 , wherein the transparent protection layer has a thickness in a range from 2 μm to 5 μm.

3. A method of manufacturing an array substrate, comprising steps of:
forming a display area and a non-display area on a substrate, a circuit bonding area being arranged within the non-display area;
forming an alignment film in the display area through a patterning process;
forming, through a patterning process, a transparent protection layer at least in a portion of the non-display area other than the circuit bonding area; and
forming, through a rubbing-imprinting process, a plurality of lines having the same orientation on a surface of the alignment film, for an ordered arrangement of liquid crystal molecules,
wherein a surface height of the transparent protection layer is lower than or equal to a surface height of the alignment film; and
wherein the steps of forming the alignment film and the transparent protection layer comprise:
coating a first resin layer on a surface of the substrate having the display area and the non-display area;
coating a second resin layer on the first resin layer;
forming a photoresist layer on a surface of the second resin layer;
forming, through a single masking and exposing process and a single development process, a second full coverage area of the photoresist layer, a second full removal area of the photoresist layer, and a partial removal area of the photoresist layer, the second full coverage area of the photoresist layer corresponding to the alignment film to be formed, the second full removal area of the photoresist layer corresponding to the circuit bonding area, and the partial removal area of the photoresist layer corresponding to the transparent protection layer to be formed;
etching a portion of the second resin layer and a portion of the first resin layer corresponding to the second full removal area of the photoresist layer;
ashing a portion of the photoresist in the partial removal area of the photoresist layer, and etching a portion of the second resin layer corresponding to the partial removal area of the photoresist layer; and
peeling off a portion of the photoresist within the second full coverage area of the photoresist layer, so that a remaining portion of the first resin layer forms the transparent protection layer.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Dong Tingze
• Wang Yujia
• Mo Jun
• Guan Peiqiang
• Zhang Zhinan

Classifications

• G02F1/133784 Primary

  by rubbing · CPC title

• G02F2201/121

  common or background · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F1/13378 Primary

  by treatment of the surface, e.g. embossing, rubbing or light irradiation (G02F1/133711, G02F1/133734, G02F1/133753 take precedence) · CPC title

• G02F2201/123

  pixel · CPC title