System and method for signal read-out using source follower feedback

US9866939B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9866939-B2
Application numberUS-201615050972-A
CountryUS
Kind codeB2
Filing dateFeb 23, 2016
Priority dateFeb 23, 2016
Publication dateJan 9, 2018
Grant dateJan 9, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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An embodiment amplifier circuit includes a pair of subcircuits that includes a first subcircuit and a second subcircuit, each of which includes a buffer amplifier and a feedback circuit that includes a feedback capacitor. The amplifier circuit also includes a pair of output terminals. The first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals that includes a first output signal and a second output signal. The amplifier circuit is configured for receiving a positive differential input signal at the first subcircuit, receiving a negative differential input signal at the second subcircuit, and receiving the pair of output signals at the pair of output terminals. The amplifier circuit is also configured for transmitting the first output signal to the feedback circuit of the first subcircuit, and transmitting the second output signal to the feedback circuit of the second subcircuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for signal read-out comprising: receiving, by an amplifier circuit, a positive differential input signal at a first subcircuit of the amplifier circuit, the first subcircuit comprising a source follower transistor; receiving, by the amplifier circuit, a negative differential input signal at a second subcircuit of the amplifier circuit, the second subcircuit comprising a source follower transistor; transmitting one of a pair of output signals as a first feedback signal to a capacitive feedback circuit of the first subcircuit, wherein the pair of output signals comprise an output signal of the first subcircuit and an output signal of the second subcircuit; transmitting one of the pair of output signals as a second feedback signal to a capacitive feedback circuit of the second subcircuit, wherein the first feedback signal is distinct from the second feedback signal; determining a target voltage transfer ratio of the amplifier circuit in accordance with a sensitivity of an external input device and in accordance with a target output sensitivity of a signal read-out for the external input device; adjusting a capacitance of the capacitive feedback circuit of the first subcircuit in accordance with the target voltage transfer ratio; and adjusting a capacitance of a capacitive feedback circuit of the second subcircuit in accordance with the target voltage transfer ratio. 2. The method of claim 1 , further comprising: selecting, in accordance with the target voltage transfer ratio, the first feedback signal from the pair of output signals; and selecting, in accordance with the target voltage transfer ratio, the second feedback signal from the pair of output signals. 3. The method of claim 2 , wherein: the transmitting the first feedback signal comprises: determining a non-feedback voltage transfer ratio; comparing the target voltage transfer ratio to the non-feedback voltage transfer ratio; and selecting, when the target voltage transfer ratio is greater than the non-feedback voltage transfer ratio, the output signal of the first subcircuit as the first feedback signal. 4. The method of claim 1 , wherein each of the first subcircuit and the second subcircuit further comprises a super source follower (SSF) stage comprising the source follower transistor. 5. The method of claim 1 , wherein each of the first subcircuit and the second subcircuit further comprises: a current bias transistor comprising a gate coupled to an output of the capacitive feedback circuit; and a feedback node coupled to an input of the capacitive feedback circuit. 6. The method of claim 5 , wherein a configurable voltage transfer ratio of each of the first subcircuit and the second subcircuit varies in accordance with an amplitude of a current variation through the current bias transistor. 7. The method of claim 1 , wherein the positive differential input signal and the negative differential input signal are generated as differential outputs of an external micro-electro-mechanical system (MEMS) device. 8. The method of claim 7 , wherein: the external MEMS device comprises an external microphone, the external microphone comprising a membrane capacitively coupled to a pair of back-plates; and the differential outputs of the external MEMS device are generated at the pair of back-plates. 9. An amplifier circuit comprising: a pair of subcircuits comprising a first subcircuit and a second subcircuit, each comprising: a buffer amplifier; and a feedback circuit comprising a feedback capacitor, wherein the first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals, the pair of output signals comprises a first output signal and a second output signal, and the amplifier circuit is configured for receiving a positive differential input signal at the first subcircuit, receiving a negative differential input signal at the second subcircuit, transmitting the first output signal to the feedback circuit of the first subcircuit, transmitting the second output signal to the feedback circuit of the second subcircuit, adjusting, in accordance with a target voltage transfer ratio, a capacitance of the feedback circuit of each of the first subcircuit and the second subcircuit, selecting, in accordance with the target voltage transfer ratio, the first output signal from a pair of output signals comprising an output of the first subcircuit and an output of the second subcircuit, and selecting, in accordance with the target voltage transfer ratio, the second output signal from the pair of output signals, wherein the second output signal is distinct from the first output signal. 10. The amplifier circuit of claim 9 , wherein the positive differential input signal and the negative differential input signal are generated as differential outputs of an external micro-electro-mechanical system (MEMS) device. 11. The amplifier circuit of claim 10 , wherein: the external MEMS device comprises an external microphone, the external microphone comprising a membrane capacitively coupled to a pair of back-plates; and the differential outputs of the external MEMS device are generated at the pair of back-plates. 12. The amplifier circuit of claim 9 , wherein each of the first subcircuit and the second subcircuit further comprises a super source follower (SSF) stage comprising the buffer amplifier. 13. The amplifier circuit of claim 9 , wherein: each of the pair of subcircuits further comprises: a current bias circuit coupled in series with the buffer amplifier, the current bias circuit comprising a current bias transistor comprising a gate coupled to an output of the feedback circuit; a subcircuit input node coupled to a gate of the buffer amplifier; a subcircuit output node; and a feedback node coupled to an input of the feedback circuit, wherein a positive input terminal of the amplifier circuit is coupled to the subcircuit input node of the first subcircuit; a negative input terminal of the amplifier circuit is coupled to the subcircuit input node of the second subcircuit; a first output terminal is coupled to the subcircuit output node of the first subcircuit; and a second output terminal is coupled to the subcircuit output node of the second subcircuit. 14. The amplifier circuit of claim 13 , wherein the current bias transistor of each of the pair of subcircuits comprises a p-channel transistor. 15. The amplifier circuit of claim 13 , wherein the current bias transistor of each of the pair of subcircuits comprises an n-channel transistor. 16. An amplifier circuit comprising: a pair of subcircuits comprising a first subcircuit and a second subcircuit, each comprising: a buffer amplifier; and a feedback circuit comprising a feedback capacitor, the first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals, the pair of output signals comprises a first output signal and a second output signal, and the amplifier circuit is configured for receiving a positive differential input signal at the first subcircuit, receiving a negative differential input signal at the second subcircuit, transmitting the first output signal to the feedback circuit of the first subcircuit, and transmitting the second output signal to the feedback circuit of the second subcircuit; a current bias circuit coupled in series with the buffer amplifier, the current bias circuit comprising a current bias transistor comprising a gate coupled to an output of the feedback circuit; a subcircuit input nod

Assignees

Inventors

Classifications

  • the amplifier being designed for audio applications · CPC title

  • Mems transducers or their use · CPC title

  • A source follower being used in a feedback circuit of an amplifier stage · CPC title

  • H04R1/04Primary

    Structural association of microphone with electric circuitry therefor (in electric hearing aids H04R25/00) · CPC title

  • using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

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What does patent US9866939B2 cover?
An embodiment amplifier circuit includes a pair of subcircuits that includes a first subcircuit and a second subcircuit, each of which includes a buffer amplifier and a feedback circuit that includes a feedback capacitor. The amplifier circuit also includes a pair of output terminals. The first subcircuit and the second subcircuit each generate a different output signal of a pair of output sign…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H04R1/04. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).