High speed low current voltage comparator

Patent metadata

Field	Value
Publication number	US-9866215-B2
Application number	US-201514870185-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

In one embodiment, a voltage comparator circuit includes a first comparator circuit to compare a first voltage and a second voltage and a second comparator circuit to compare the first voltage and the second voltage. The voltage comparator circuit may include charge storage circuitry and positive feedback circuitry. Such circuitry may boost current within the first and second comparator circuits to enable the voltage comparator circuit to output a comparison decision within a delay threshold in response to input transitions within a slew rate threshold.

First claim

What is claimed is:

1. An apparatus comprising:
a first comparator having a first common gate input stage with a first input terminal to receive a first voltage and a second input terminal to receive a second voltage, a first capacitor coupled between the first input terminal and a common gate connection of the first common gate input stage, the first common gate input stage to output a first comparison signal, and a first feedback circuit to provide a first boost current to the first common gate input stage responsive to a first value of the first comparison signal and to pull down a level of the first comparison signal responsive to a first value of a second comparison output signal, the first comparator to output a first comparison output signal based on the first comparison signal; and
a second comparator having a second common gate input stage with a first input terminal to receive the second voltage and a second input terminal to receive the first voltage, and a second capacitor coupled between the first input terminal of the second common gate input stage and a common gate connection of the second common gate input stage, the second common gate input stage to output a second comparison signal, the second comparator to output the second comparison output signal based on the second comparison signal.

2. The apparatus of claim 1 , further comprising a second feedback circuit to provide a second boost current to the second common gate input stage responsive to a first value of the second comparison signal and to pull down a level of the second comparison signal responsive to a first value of the first comparison output signal.

3. The apparatus of claim 1 , wherein the first comparator further comprises:
a first inverter to receive the first comparison signal and to invert the first comparison signal, the first inverter to be powered by the first voltage; and
a second inverter to receive the inverted first comparison signal and to output the first comparison output signal, the second inverter to be powered by the second voltage.

4. The apparatus of claim 1 , wherein the first comparator further comprises:
a first delay circuit to receive the first comparison output signal and to output a first control signal to enable the first feedback circuit to provide the first boost current.

5. The apparatus of claim 4 , wherein the first delay circuit comprises:
a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal to receive the first comparison output signal and a second terminal coupled to a resistor-capacitor (RC) network; and
a second MOSFET having a gate terminal to receive the first comparison output signal and a second terminal coupled to the resistor of the RC network, the RC network to provide the first control signal to the first feedback circuit.

6. The apparatus of claim 1 , wherein the first comparator is to generate the first comparison output signal within 100 nanoseconds of a change in at least one of the first voltage and the second voltage.

7. The apparatus of claim 1 , wherein the first feedback circuit includes a first branch, the first branch to be disabled based on a state of the second comparison output signal, wherein disabling the first branch is to reduce power consumption of the apparatus.

8. The apparatus of claim 7 , wherein the first branch comprises:
a first MOSFET having a gate terminal to receive the second comparison output signal, a first terminal coupled to a first current source and a second MOSFET, and a second terminal coupled to an output of the first common gate input stage.

9. The apparatus of claim 7 , wherein the first feedback circuit further includes a second branch comprising a third MOSFET having a gate terminal to receive the first comparison signal, a first terminal coupled to a fourth MOSFET, and a second terminal coupled to the first common gate input stage, wherein the fourth MOSFET is to be gated by a first control signal received from a first delay circuit.

10. The apparatus of claim 1 , further comprising:
a logic circuit to monitor for a transition in at least the first comparison output signal and to generate an output signal based thereon; and
a rectifier circuit to provide a maximum one of the first voltage and the second voltage to the logic circuit.

11. The apparatus of claim 10 , wherein the apparatus comprises an integrated circuit (IC) including a voltage regulator to receive and regulate a selected one of the first voltage and the second voltage, based on the output signal.

12. An apparatus comprising:
a voltage comparator circuit including a first comparator circuit to compare a first voltage and a second voltage and a second comparator circuit to compare the first voltage and the second voltage, the voltage comparator circuit including charge storage circuitry and positive feedback circuitry to boost current within the first and second comparator circuits to enable the voltage comparator circuit to output a comparison decision within a delay threshold in response to input transitions within a slew rate threshold, wherein the first comparator circuit comprises:
a first common gate input stage to receive the first voltage and the second voltage and to generate a first comparison value based on the comparison of the first voltage and the second voltage, wherein the first common gate input stage comprises:
a first metal oxide semiconductor field effect transistor (MOSFET) having a first terminal to couple to the first voltage, a second terminal to couple to a first current source, and a gate terminal coupled to a gate terminal of a second MOSFET, the second terminal of the first MOSFET to further couple to the gate terminal of the first MOSFET; and
the second MOSFET having a first terminal to couple to the second voltage and a second terminal to output the first comparison value; and

a first feedback circuit to control a level of the first comparison value, wherein the first comparator circuit is to output a first comparison output signal based on the first comparison value; and

wherein the second comparator circuit comprises:
a second common gate input stage to receive the first voltage and the second voltage and to generate a second comparison value based on the comparison of the first voltage and the second voltage; and
a second feedback circuit to control a level of the second comparison value, wherein the second comparator circuit is to output a second comparison output signal based on the second comparison value, wherein the first comparison output signal and the second comparison output signal comprise the comparison decision.

13. The apparatus of claim 12 , wherein the first feedback circuit comprises a third MOSFET having a first terminal to couple to a second current source, a second terminal coupled to the second terminal of the second MOSFET, and a gate terminal to receive the second comparison output signal.

14. The apparatus of claim 12 , further comprising a first capacitor coupled to the gate terminal and the first terminal of the first MOSFET.

15. The apparatus of claim 12 , further comprising a logic circuit to receive the first comparison output signal and the second comparison output signal and to output an output signal based thereon.

16. An apparatus comprising:
a voltage regulator to receive a first voltage from a first voltage source, a second voltage from a second voltage source, a comparator to compare the first voltage and the second voltage, the comparator comprising:
a first comparator having a first common gate input stage with a first input terminal to receive

Assignees

• Silicon Lab Inc

Inventors

• Atkinson Nicholas Montgomery
• Kallam Praveen
• Elsayed Mohamed Mostafa

Classifications

• H03K5/06

  by the use of delay lines or other analogue delay elements · CPC title

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title