System and method for a low noise amplifier

Patent metadata

Field	Value
Publication number	US-9866177-B2
Application number	US-201615130488-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Mar 27, 2014
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.

First claim

What is claimed is:

1. A low noise amplifier (LNA) comprising:
a plurality of separate input terminals;
a plurality of transistors, wherein each transistor comprises:
a conduction path, and
a control terminal coupled to one of the plurality of separate input terminals;

an output network coupled to a first reference terminal, the conduction path of each of the plurality of transistors, and a single output of the LNA, wherein the output network comprises a plurality of matching networks, each matching network of the plurality of matching networks is coupled between the single output of the LNA and the conduction path of a corresponding transistor of the plurality of transistors, and each matching network of the plurality of matching networks comprises a different passband; and
a degeneration element having a first end coupled to a second reference terminal and a second end coupled to the conduction path of each of the plurality of transistors.

2. The LNA of claim 1 , wherein the degeneration element comprises an inductor.

3. The LNA of claim 1 , wherein the output network comprises an LC tank.

4. The LNA of claim 1 , wherein the output network comprises a complex impedance substantially matched to an impedance coupled to the single output of the LNA.

5. The LNA of claim 1 , wherein the output network has a first impedance in-band and a second impedance out of band, wherein the second impedance is greater than the first impedance.

6. The LNA of claim 5 , wherein the first impedance is substantially matched to an impedance coupled to the single output of the LNA.

7. The LNA of claim 1 , further comprising a bias network coupled to the control terminal of each of the plurality of transistors, wherein the bias network is configured to activate one transistor of the plurality of transistors at a time.

8. A method of operating a low noise amplifier (LNA), the method comprising:
receiving a first signal at a first input terminal of a plurality of separate input terminals of the LNA;
receiving a second signal at a second input terminal of the plurality of separate input terminals of the LNA;
amplifying the first signal at a first transistor of a plurality of transistors of the LNA;
amplifying the second signal at a second transistor of a plurality of transistors of the LNA;
combining the first and second signals at a shared output line of the LNA, the shared output line being coupled to conduction terminals of the first and second transistors; and
supplying the first and second signals to a processing circuit on a single coupling line coupled to the shared output line, wherein the LNA further comprises
an output matching network coupled to a first reference terminal, a conduction path of each of the plurality of transistors, and the shared output line, wherein the output matching network comprises a plurality of matching networks, each matching network of the plurality of matching networks is coupled between the shared output line and a conduction terminal of a corresponding transistor of the plurality of transistors, and each matching network of the plurality of matching networks comprises a different passband, and
a degeneration element having a first end coupled to a second reference terminal and a second end coupled to the conduction path of each of the plurality of transistors.

9. The method of claim 8 , wherein the first transistor, the second transistor, and the shared output line are formed on a single semiconductor die.

10. The method of claim 8 , wherein receiving the first signal and receiving the second signal are performed simultaneously and the first and second signals are supplied to the processing circuit simultaneously.

11. The method of claim 8 , wherein receiving the first and second signals comprises receiving first and second signals from a filter bank, the filter bank coupled to an antenna circuit, and wherein the filter bank, the first transistor, and the second transistor are disposed in proximity to one another on a same chip in proportion to a size of the same chip.

12. The method of claim 11 , wherein disposed in proximity comprises disposed immediately adjacent on a same chip.

13. The method of claim 11 , wherein disposed in proximity comprises disposed within 10% of a longest dimension of the same chip.

14. The method of claim 11 , wherein the single coupling line comprises a coaxial cable and the processing circuit is disposed on the same chip distant from the antenna circuit, the filter bank, the first transistor, and the second transistor.

15. The method of claim 8 , wherein combining the first and second signals at the shared output line of the LNA comprises:
receiving the first and second signals by the output matching network from the first and second transistors after amplifying the first and second signals; and
substantially matching an output impedance of the shared output line with the output matching network, the output matching network comprising outputs coupled to the shared output line.

16. The method of claim 8 , further comprising activating only one of the first transistor or the second transistor at a time in order to amplifying either the first signal or the second signal.

17. A low noise amplifier (LNA) comprising:
a plurality of separate input terminals;
a plurality of transistors, wherein each transistor comprises:
a conduction path, and
a control terminal coupled to one of the plurality of separate input terminals; and

an output network comprising a plurality of matching networks, each matching network of the plurality of matching networks comprising:
an LC tank having a first tank terminal coupled to a first reference terminal, a second tank terminal coupled to the conduction path of a corresponding transistor of the of the plurality of transistors, and
an LC network coupled between the LC tank and a single output of the LNA.

18. The LNA of claim 17 , further comprising a plurality of degeneration circuits, wherein each degeneration circuit of the plurality of degeneration circuits are coupled between a respective conduction path of each transistor of the plurality of transistors and a second reference terminal.

19. The LNA of claim 17 , wherein each matching network of the plurality of matching networks has a first impedance in-band and a second impedance out of band, wherein the second impedance is greater than the first impedance.

20. The LNA of claim 19 , wherein, for each matching network of the plurality of matching networks, the first impedance is substantially matched to an impedance coupled to the single output of the LNA.

21. The LNA of claim 19 , wherein each transistor of the plurality of transistors is a bipolar junction transistor (BJT), and the conduction path of each transistor of the plurality of transistors is connected between a collector and an emitter of each transistor of the plurality of transistors.

22. The LNA of claim 17 , wherein:
a first matching network of the plurality of matching networks comprises a lowpass frequency response;
a second matching network of the plurality of matching networks comprises a bandpass frequency response; and
a third matching network of the plurality of matching networks comprises a highpass frequency response.

23. The LNA of claim 17 , wherein each matching network of the plurality of matching networks comprises a different passband.

24. The LNA of claim 1 , wherein each transistor of the plurality of tr

Assignees

• Infineon Technologies Ag

Inventors

• Kehrer Daniel
• Oliveira Paulo
• Leitner Thomas

Classifications

• H03F2203/21109

  An input signal being distributed by switching to a plurality of paralleled power amplifiers · CPC title

• H03F2200/111

  the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not · CPC title

• H04B1/006

  using switches for selecting the desired band (H04B1/0057 takes precedence) · CPC title

• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title