Galvanic isolator and circuit using galvanic isolation

Patent metadata

Field	Value
Publication number	US-9866126-B2
Application number	US-201514922269-A
Country	US
Kind code	B2
Filing date	Oct 26, 2015
Priority date	Oct 26, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A method and apparatus for isolating voltages while transmitting data signals. In one embodiment of the method, a modulation circuit modulates a carrier signal using an input data signal. A demodulation circuit receives the modulated carrier signal via a first capacitor coupled in series between the modulation circuit and the demodulation circuit. The demodulation circuit also receives the carrier signal via a second capacitor coupled in series between the demodulation circuit and the circuit that generates the carrier signal. The demodulation circuit demodulates the modulated carrier signal using the carrier signal.

First claim

What is claimed is:

1. An apparatus comprising:
a first switch coupled between a first voltage node and a common node;
a second switch coupled between the common node and a second voltage node;
a third switch coupled between the first voltage node and another common node;
a fourth switch coupled between the other common node and the second voltage node;
an inductor coupled to the common node and the other common node
a first circuit for generating a pulse width modulation (PWM) signal;
a second circuit for generating complementary, non-overlapping first and second PWM signals in response to the generation of the PWM signal, wherein the first and second PWM signals are used for controlling the first and second switches, respectively;
a first galvanic isolation (GI) circuit coupled between the first circuit and the second circuit.

2. An apparatus comprising:
a first switch coupled between a first voltage node and a common node;
a second switch coupled between the common node and a second voltage node;
a first circuit for generating a pulse width modulation (PWM) signal;
a second circuit for generating complementary, non-overlapping first and second PWM signals in response to the generation of the PWM signal, wherein the first and second PWM signals are used for controlling the first and second switches, respectively;
a first galvanic isolation (GI) circuit coupled between the first circuit and the second circuit;
a first driver comprising an output node coupled to the first switch;
a second GI circuit coupled between the second circuit and an input node to the first driver.

3. The apparatus of claim 2 further comprising a third GI circuit coupled between the output node of the first driver and the second circuit.

4. The apparatus of claim 1 wherein the first switch comprises a first silicon carbide transistor and a first silicon carbide diode, and wherein the second switch comprises a second carbide transistor and a second silicon carbide diode.

5. An apparatus comprising:
a first switch coupled between a first voltage node and a common node;
a second switch coupled between the common node and a second voltage node;
a first circuit for generating a pulse width modulation (PWM) signal;
a second circuit for generating complementary, non-overlapping first and second PWM signals in response to the generation of the PWM signal, wherein the first and second PWM signals are used for controlling the first and second switches, respectively;
a first galvanic isolation (GI) circuit coupled between the first circuit and the second circuit;
wherein the first GI circuit comprises a first capacitor coupled in series between the first circuit and the second circuit;
wherein the first GI circuit comprises a modulator and a demodulator with the first capacitor coupled in series between the modulator and the demodulator, wherein the modulator is configured to receive and modulate a first carrier signal using the PWM signal.

6. The apparatus of claim 5 wherein the first GI circuit comprises a first carrier signal generator and a second capacitor coupled in series between and the first carrier signal generator and the demodulator, wherein the first carrier signal generator is configured to generate the first carrier signal.

7. The apparatus of claim 6 wherein the first GI circuit further comprises a first low pass filter (LPF) circuit coupled in series between the demodulator and the second circuit, wherein the LPF circuit is configured to filter an output signal of the demodulator.

8. An apparatus comprising:
a first galvanic isolation (GI) circuit comprising:
a carrier signal generator for generating a carrier signal;
a modulator for modulating the carrier signal using a signal received at an input of the modulator;
a demodulator;
a first capacitor coupled in series between the modulator and the demodulator;
a second capacitor coupled in series between the carrier signal generator and the demodulator.

9. The apparatus of claim 8 wherein the demodulator is configured to demodulate a signal received from the modulator via the first capacitor, using a signal received from the carrier signal generator via the second capacitor.

10. The apparatus of claim 8 wherein the first GI circuit further comprises a low pass filter (LPF) coupled to the demodulator for low pass filtering an output signal of the demodulator.

11. The apparatus of claim 8 wherein the first GI circuit further comprises:
a first ground node, wherein the modulator and the carrier signal generator are coupled to the first ground node;
a third capacitor coupled in series between the first ground node and the demodulator.

12. The apparatus of claim 8 further comprising:
a first circuit for generating a pulse width modulation (PWM) signal;
wherein the first GI circuit is coupled to the first circuit;
wherein the signal is the PWM signal.

13. The apparatus of claim 11 further comprising:
a power converter comprising:
a first switch coupled between a first voltage node and a common node;
a second switch coupled between the common node and a second voltage node;
an inductor coupled to the common node;

wherein the first GI circuit is coupled in series between the first circuit and the power converter.

14. The apparatus of claim 13 wherein the first switch comprises a first silicon carbide transistor and a first silicon carbide diode, and wherein the second switch comprises a second carbide transistor and a second silicon carbide diode.

15. The apparatus of claim 13 wherein the power converter further comprises:
a second circuit coupled to receive an output signal from the first GI circuit;
a first driver comprising an output node coupled to the first switch;
a second GI circuit coupled between the second circuit and an input node of the first driver;
a third GI circuit coupled between the second circuit and the output node of the first driver;
wherein the second circuit is configured to generate first and second PWM signals for controlling the first and second switches, respectively;
wherein the second circuit generates the first and second PWM signals as a function of the first GI circuit output signal, wherein the first and second PWM signals are complementary and non-overlapping.

16. A method comprising:
a carrier signal generating circuit generating a carrier signal;
a modulation circuit receiving an input signal and modulating the carrier signal using the input signal;
a demodulation circuit demodulating a signal it receives from the modulation circuit via a first capacitor coupled in series between the modulation circuit and the demodulation circuit, using a signal the demodulation circuit receives from the carrier signal generating circuit via a second capacitor, which is coupled in series between the carrier signal generating circuit and the demodulation circuit.

17. The method of claim 15 where in the input signal comprises a pulse width modulation signal.

18. The method of claim 17 further comprising:
generating complementary first and second pulse width modulation (PWM) signals as a function of the pulse width modulation signal;
wherein the first and second PWM signals are used for controlling first and second switches, respectively of a half-bridge or full-bridge circuit;
wherein the first PWM signal switches between states, wherein the state of the first PWM signal depends on a state of the second switch;
wherein the second PWM signal switches between states, wherein the state of the second PWM signal state depends on a s

Assignees

• Renesas Electronics America Inc

Inventors

• Sato Tetsuo

Classifications

• H02M3/33523 Primary

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• H02M3/33546 Primary

  with automatic control of the output voltage or current (H02M3/33561 takes precedence) · CPC title