Reduction of frequency variation for ripple based, constant-on-time DC-DC converters

Patent metadata

Field	Value
Publication number	US-9866115-B2
Application number	US-201615088597-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed.

First claim

What is claimed is:

1. A circuit for controlling frequency variation for a ripple based, constant on-time DC-DC converter, the circuit comprising:
a set/reset (SR) latch;
a comparator configured to set the SR latch; and
an on-time and frequency variation controller configured to reset the SR latch, wherein the on-time and frequency variation controller includes:
a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage.

2. The circuit of claim 1 , wherein the feedback loop comprises a circuit configured to generate a slope gain value and to increase the rate at which the ramp voltage increases as a function of the slope gain value.

3. The circuit of claim 2 , wherein the feedback loop comprises a sample and hold circuit, a divider, and a multiplier.

4. The circuit of claim 3 , wherein the sample and hold circuit is configured to output a sampled and held value to the divider, the divider is configured to divide the sampled and held value by the threshold voltage to produce the slope gain value, and the multiplier is configured to multiply by the slope gain value.

5. An inductor current ripple based, constant on-time DC-DC boost converter comprising the circuit of claim 1 .

6. An inductor current ripple based, constant on-time DC-DC buck converter comprising the circuit of claim 1 .

7. An output voltage ripple based, constant on-time DC-DC buck converter comprising the circuit of claim 1 .

8. A method for controlling frequency variation for a ripple based, constant on-time DC-DC converter, the method comprising:
setting a set/reset (SR) latch in response to an output voltage of the DC-DC converter, wherein setting the SR latch involves increasing the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage; and
resetting the SR latch in response to the ramp voltage exceeding the threshold voltage.

9. The method of claim 8 wherein increasing the rate at which the ramp voltage increases involves sampling and holding the ramp voltage to capture a peak ramp voltage.

10. The method of claim 9 wherein increasing the rate at which the ramp voltage increases involves dividing the peak ramp voltage by the threshold voltage to generate a slope gain value.

11. The method of claim 10 wherein increasing the rate at which the ramp voltage increases involves multiplying a voltage by the slope gain value.

12. An inductor current ripple based, constant on-time DC-DC boost converter configured to implement the method of claim 8 .

13. An inductor current ripple based, constant on-time DC-DC buck converter configured to implement the method of claim 8 .

14. An output voltage ripple based, constant on-time DC-DC buck converter configured to implement the method of claim 8 .

15. A circuit for controlling frequency variation for an inductor current ripple based, constant on-time DC-DC converter, the circuit comprising:
a set/reset (SR) latch;
a comparator configured to set the SR latch; and
an on-time and frequency variation controller configured to reset the SR latch, wherein the on-time and frequency variation controller includes:
a comparator having a first input and a second input;
a capacitor connected to the second input of the comparator and configured to provide a ramp voltage to the comparator;
a reset switch connected to the second input of the comparator;
an operational transconductance amplifier (OTA) connected to the second input of the comparator and having a first input and a second input; and
a feedback loop connected between the second input of the comparator and the first input of the OTA and configured to increase the rate at which the ramp voltage increases.

16. The circuit of claim 15 , wherein the feedback loop comprises a circuit configured to generate a slope gain value and to increase the rate at which the ramp voltage increases as a function of the slope gain value.

17. The circuit of claim 16 , wherein the feedback loop comprises a sample and hold circuit, a divider, and a multiplier.

18. The circuit of claim 17 , wherein the sample and hold circuit is configured to output a sampled value to the divider, the divider is configured to divide the sampled value by the threshold voltage to produce the slope gain value, and the multiplier is configured to multiply by the slope gain value.

19. An inductor current ripple based, constant on-time DC-DC boost converter comprising the circuit of claim 15 .

20. An inductor current ripple based, constant on-time DC-DC buck converter comprising the circuit of claim 15 .

Assignees

• Nxp Bv

Inventors

• Jing Yue
• Dashtestani Ahmad
• Chan Shufan

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M3/1563

  without using an external clock (H02M3/158 takes precedence) · CPC title

• H02M1/15 Primary

  using active elements · CPC title