Schottky diode

US9865750B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9865750-B2
Application numberUS-201514810678-A
CountryUS
Kind codeB2
Filing dateJul 28, 2015
Priority dateSep 11, 2011
Publication dateJan 9, 2018
Grant dateJan 9, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a drift layer having a first surface with an active region and a plurality of junction barrier element recesses, the drift layer being doped with a doping material of a first conductivity type and associated with an edge termination region that is substantially laterally adjacent the active region, wherein the edge termination region comprises a plurality of guard rings; a Schottky layer over the active region of the first surface to form a Schottky junction; a plurality of first doped regions that extend into the drift layer about corresponding ones of the plurality of junction barrier element recesses wherein the plurality of first doped regions are doped with a doping material of a second conductivity type, which is opposite the first conductivity type, and form an array of junction barrier elements in the drift layer below the Schottky junction; and a well formed in the drift layer in the edge termination region, the well having the guard rings and being doped with the doping material of the second conductivity type where the plurality of the guard rings are formed in the well, wherein the guard rings are coplanar with the junction barrier element recesses. 2. The semiconductor device of claim 1 wherein each of the plurality of junction barrier element recesses has at least one side and a bottom and each of the plurality of first doped regions extends into the drift layer about the at least one side and the bottom of a corresponding one of the plurality of junction barrier element recesses. 3. The semiconductor device of claim 1 wherein junction barrier elements in the array of junction barrier elements are separated from one another within the drift layer. 4. The semiconductor device of claim 1 wherein a depth of at least one of the plurality of junction barrier element recesses is at least 0.1 microns. 5. The semiconductor device of claim 4 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns. 6. The semiconductor device of claim 1 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns. 7. The semiconductor device of claim 1 wherein at least some of the plurality of the guard rings are second doped regions that extend into the drift layer, and the second doped regions are doped with the doping material of the second conductivity type. 8. The semiconductor device of claim 7 wherein the guard rings in the plurality of the guard rings are separated from each other within the drift layer. 9. The semiconductor device of claim 1 wherein the Schottky layer is formed from a low barrier height capable metal. 10. The semiconductor device of claim 9 wherein the low barrier height capable metal of the Schottky layer comprises tantalum. 11. The semiconductor device of claim 9 wherein the low barrier height capable metal of the Schottky layer comprises at least one of a group consisting of titanium, chromium, and aluminum. 12. The semiconductor device of claim 9 wherein the low barrier height capable metal of the Schottky layer consists essentially of tantalum. 13. The semiconductor device of claim 1 wherein the Schottky junction has a barrier height of less than 0.9 electron volts. 14. The semiconductor device of claim 1 wherein the drift layer is formed over a thinned substrate that was thinned after the drift layer was formed and a cathode contact is formed over a bottom surface of the thinned substrate. 15. The semiconductor device of claim 1 wherein the drift layer is predominantly doped with the doping material of the first conductivity type in a graded fashion wherein the drift layer has a lower doping concentration near the first surface and an intentionally higher doping concentration near a second surface of the drift layer, the second surface being substantially opposite the first surface. 16. The semiconductor device of claim 1 wherein the drift layer comprises silicon carbide. 17. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a Schottky diode. 18. The semiconductor device of claim 17 wherein when forward biased, the semiconductor device supports a DC current density of at least 440 amperes/cm. 19. The semiconductor device of claim 17 wherein when forward biased, the semiconductor device supports a DC current density of at least 500 amperes/cm. 20. The semiconductor device of claim 17 wherein a ratio of DC forward biased current density to reverse biased anode-cathode capacitance is at least 0.275 ampere/pico-Farad (A/pF), wherein a reverse biased anode-cathode voltage is determined when the Schottky diode is reverse biased to a point where the active region is essentially fully depleted. 21. The semiconductor device of claim 17 wherein a ratio of DC forward biased current density to reverse biased anode-cathode capacitance is at least 0.3 ampere/pico-Farad (A/pF), wherein a reverse biased anode-cathode voltage is determined when the Schottky diode is reverse biased to a point where the active region is essentially fully depleted. 22. The semiconductor device of claim 17 wherein a ratio of DC forward biased current density to reverse biased anode-cathode capacitance is at least 0.35 ampere/pico-Farad (A/pF), wherein a reverse biased anode-cathode voltage is determined when the Schottky diode is reverse biased to a point where the active region is essentially fully depleted. 23. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a silicon carbide Schottky diode. 24. The semiconductor device of claim 1 , wherein the Schottky layer is disposed within at least one recess of the plurality of junction barrier element recesses.

Assignees

Inventors

Classifications

  • relative to the surface, e.g. recessed, protruding · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Plan-view shape, i.e. in top view · CPC title

  • Bond pads specially adapted therefor · CPC title

  • H01L29/872Primary

    Electricity · mapped topic

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What does patent US9865750B2 cover?
The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.
Who is the assignee on this patent?
Cree Inc
What technology area does this patent fall under?
Primary CPC classification H01L29/872. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).