III-nitride transistor with trench gate

Patent metadata

Field	Value
Publication number	US-9865725-B2
Application number	US-201615099390-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	Apr 14, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A transistor includes a stack of III-nitride semiconductor layers, the stack having a frontside and a backside, a source electrode in contact with the frontside of the stack, a drain electrode in contact with the backside of the stack, a trench extending through a portion of the stack, the trench having a sidewall, and a gate structure formed in the trench, including an AlN layer formed on the sidewall of the trench, an insulating cap layer formed on the AlN layer, and a gate electrode formed on the insulator cap layer and covering the sidewall of the trench.

First claim

What is claimed is:

1. A transistor comprising:
a drain electrode;
a drain contact layer in contact with the drain electrode;
a channel layer on the drain contact layer;
a p− layer of AlGaN or GaN on the channel layer;
a source contact layer on the p− layer;
a source electrode in contact with the source contact layer;
a trench extending through the source contact layer and the p− layer, the trench having a vertical sidewall; and
a gate structure formed in the trench comprising:
an AlN layer formed on the sidewall of the trench;
an insulating cap layer formed on the AlN layer; and
a gate electrode formed on the insulator cap layer and covering the sidewall of the trench;
wherein a bottom of the AlN layer does not extend below a bottom of the p− layer.

2. The transistor of claim 1 wherein:
the drain contact layer comprises n+ GaN;
the channel layer comprises n− GaN;
the p− layer comprises AlGaN or GaN; and
the source contact layer comprises n+ GaN.

3. The transistor of claim 1 , wherein the AlN layer comprises
a single-crystalline AlN layer formed on the sidewall of the trench; and
a poly-crystalline AlN layer formed on the single-crystalline AlN layer.

4. The transistor of claim 3 :
wherein the single-crystalline AlN layer ranges from about 0.5 nm to 2 nm thick; and
wherein the poly-crystalline AlN layer ranges from about 5 nm to 50 nm thick.

5. The transistor of claim 3 wherein the single-crystalline AlN layer is grown by MOCVD or MBE.

6. The transistor of claim 3 wherein the poly-crystalline AlN layer is grown by MOCVD or MBE.

7. The transistor of claim 3 :
wherein the single-crystalline AlN layer is grown by MOCVD at a temperature between 600° C. and 1000° C.; and
wherein the poly-crystalline AlN layer is grown by MOCVD at a temperature between 600° C. and 1000° C.

8. The transistor of claim 1 further comprising:
a second GaN channel layer between the AlN layer and the sidewall of the trench;
wherein the second GaN channel layer is in contact with the channel layer.

9. The transistor of claim 8 wherein the second GaN channel layer ranges from about 1 nm to 10 nm thick.

10. The transistor of claim 8 wherein the second GaN channel layer is grown by MOCVD or MBE.

11. The transistor of claim 1 :
wherein the trench has a width ranging between 0.5 μm to 5 μm.

12. A method of fabricating a transistor comprising:
forming a drain contact layer;
forming a channel layer on the drain contact layer;
forming a p− layer on the channel layer;
forming a source contact layer on the p− layer;
forming a source electrode on the source contact layer;
forming a drain electrode on the drain contact layer;
forming a trench extending through the source contact layer and the p− layer, the trench having a vertical sidewall; and
forming a gate structure in the trench comprising:
forming an AlN layer on the sidewall of the trench;
forming an insulating cap layer on the AlN layer; and
forming a gate electrode on the insulator cap layer and covering the sidewall of the trench;
wherein a bottom of the AlN layer does not extend below a bottom of the p− layer.

13. The method of claim 12 wherein:
the drain contact layer comprises n+ GaN;
the channel layer comprises n− GaN;
the p− layer comprises AlGaN or GaN; and
the source contact layer comprises n+ GaN.

14. The method of claim 12 , wherein forming the AlN layer comprises
forming a single-crystalline AlN layer on the sidewall of the trench; and
forming a poly-crystalline AlN layer on the single-crystalline AlN layer.

15. The method of claim 14 :
wherein the single-crystalline AlN layer ranges from about 0.5 nm to 2 nm thick; and
wherein the poly-crystalline AlN layer ranges from about 5 nm to 50 nm thick.

16. The method of claim 14 wherein the single-crystalline AlN layer is grown by MOCVD or MBE.

17. The method of claim 14 wherein the poly-crystalline AlN layer is grown by MOCVD or MBE.

18. The method of claim 14 :
wherein the single-crystalline AlN layer is grown by MOCVD at a temperature between 600° C. and 1000° C.; and
wherein the poly-crystalline AlN layer is grown by MOCVD at a temperature between 600° C. and 1000° C.

19. The method of claim 12 further comprising:
forming a second GaN channel layer between the AlN layer and the sidewall of the trench;
wherein the second GaN channel layer is in contact with the channel layer.

20. The method of claim 19 wherein the second GaN channel layer ranges from about 1 nm to 10 nm thick.

21. The method of claim 19 wherein the second GaN channel layer is grown by MOCVD or MBE.

22. The method of claim 12 :
wherein forming the trench comprises forming the trench to have a width ranging between 0.5 μm to 5 μm.

23. A transistor comprising:
a source electrode;
a drain electrode;
a drain contact layer comprising n+ GaN, the drain contact layer in contact with the drain electrode;
a channel layer of n− GaN on the drain contact layer;
a p− layer of AlGaN or GaN on the channel layer; and
a source contact layer of n+ GaN on the p− layer, the source contact layer in contact with the source electrode;
a trench extending through the source contact layer and the p− layer, the trench having a vertical sidewall; and
a gate structure formed in the trench comprising:
an AlN layer formed on the sidewall of the trench;
an insulating cap layer formed on the AlN layer; and
a gate electrode formed on the insulator cap layer and covering the sidewall of the trench;
wherein a bottom of the AlN layer does not extend below a bottom of the p− layer.

24. The transistor of claim 23 , wherein the AlN layer comprises
a single-crystalline AlN layer formed on the sidewall of the trench; and
a poly-crystalline AlN layer formed on the single-crystalline AlN layer.

25. The transistor of claim 24 further comprising:
a second GaN channel layer between the AlN layer and the sidewall of the trench;
wherein the second GaN channel layer is in contact with the channel layer.

26. The transistor of claim 25 :
wherein the single-crystalline AlN layer ranges from about 0.5 nm to 2 nm thick;
wherein the poly-crystalline AlN layer ranges from about 5 nm to 50 nm thick; and
wherein the second GaN channel layer ranges from about 1 nm to 10 nm thick.

27. The transistor of claim 24 :
wherein the n+ GaN drain contact layer has a doping concentration greater than 10 17 cm −3 and less than 10 21 cm −3 ;
wherein the channel layer has a doping concentration typically in the range of 10 15 cm 3 to 10 17 cm-3;
wherein the p− type GaN layer has a doping concentration between 10 17 cm −3 to 10 20 cm −3 ; and
wherein the n+ GaN source layer has a doping concentration greater than 10 17 cm −3 and less than 10 21 cm −3 .

28. The transistor of claim 27 :
wherein the channel layer has a thickness in the range of 0.5 μm to 50 μm;
wherein the p− type GaN layer has a thickness in the range of 0.1 μm to 10 μm; and
wherein the n+ GaN source layer has a thickness in the range of 0.01 μm to 1 μm.

29. The transistor of claim 23 :
wherein the trench has a width ranging between 0.5 μm to 5 μm.

Assignees

• Hrl Lab Llc

Inventors

• Chu Rongming

Classifications

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title