Printed capacitors

US9865600B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9865600-B2
Application numberUS-201615225964-A
CountryUS
Kind codeB2
Filing dateAug 2, 2016
Priority dateJun 18, 2014
Publication dateJan 9, 2018
Grant dateJan 9, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capacitor of the plurality of printed capacitors can be a horizontal or a vertical capacitor. Each printed capacitor can include a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors.

First claim

Opening claim text (preview).

What is claimed: 1. A device comprising: a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. 2. The device of claim 1 , wherein one or more of the capacitors of the plurality of electrically connected capacitors are stacked-plate capacitors. 3. The device of claim 1 , wherein one or more of the capacitors of the plurality of electrically connected capacitors are trench capacitors. 4. The device of claim 1 , wherein two or more of the capacitors of the plurality of electrically connected capacitors are electrically connected in parallel. 5. The device of claim 1 , wherein two or more of the capacitors of the plurality of electrically connected capacitors are electrically connected in series. 6. The device of claim 1 , wherein each printed capacitor includes a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors. 7. A wafer of printable capacitors, the wafer comprising: a source substrate; a first sacrificial layer on a process side of the source substrate; a first set of printable capacitors on the first sacrificial layer; a second sacrificial layer on the first set of printable capacitors; a second set of printable capacitors on the second sacrificial layer; and wherein each printed capacitor includes a plurality of electrically connected capacitors. 8. The device of claim 7 , wherein one or more of the capacitors of the plurality of electrically connected capacitors are stacked-plate capacitors. 9. The device of claim 7 , wherein one or more of the capacitors of the plurality of electrically connected capacitors are trench capacitors. 10. The device of claim 7 , wherein two or more of the capacitors of the plurality of electrically connected capacitors are electrically connected in parallel. 11. The device of claim 7 , wherein two or more of the capacitors of the plurality of electrically connected capacitors are electrically connected in series. 12. The device of claim 7 , wherein each printed capacitor includes a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors. 13. A method for assembling a plurality of capacitors on a receiving surface of a substrate, the method comprising: contacting a first capacitor of the plurality of capacitors with a transfer device having a contact surface, thereby temporarily binding the capacitor to the contact surface such that the contact surface has the capacitor temporarily disposed thereon; contacting the first capacitor disposed on the contact surface of the transfer device with the receiving surface of the substrate; separating the contact surface of the transfer device and the capacitor, wherein the capacitor is transferred onto the receiving surface, thereby assembling the capacitor on the receiving surface of the substrate; contacting a second capacitor of the plurality of capacitors with the transfer device, thereby binding the second capacitor to the contact surface such that the contact surface has the second capacitor disposed thereon; contacting the second capacitor disposed on the contact surface of the transfer device with a surface of the first capacitor assembled on the receiving surface of the substrate; and separating the contact surface of the transfer device and the second capacitor, wherein the second capacitor is transferred onto the capacitor assembled on the receiving surface of the substrate, thereby assembling the second capacitor on the capacitor assembled on the receiving surface of the substrate; and wherein each first and second printed capacitor includes a plurality of electrically connected capacitors. 14. The device of claim 13 , wherein one or more of the capacitors of the plurality of electrically connected capacitors are stacked-plate capacitors. 15. The device of claim 13 , wherein one or more of the capacitors of the plurality of electrically connected capacitors are trench capacitors. 16. The device of claim 13 , wherein two or more of the capacitors of the plurality of electrically connected capacitors are electrically connected in parallel. 17. The device of claim 13 , wherein two or more of the capacitors of the plurality of electrically connected capacitors are electrically connected in series. 18. The device of claim 13 , wherein each printed capacitor includes a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors.

Assignees

Inventors

Classifications

  • Die-attach connectors and bond wires · CPC title

  • for antennas · CPC title

  • between stacked chips · CPC title

  • used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

  • used to support diced chips prior to mounting · CPC title

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Frequently asked questions

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What does patent US9865600B2 cover?
A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capaci…
Who is the assignee on this patent?
X Celeprint Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/101. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).