Alignment in the packaging of integrated circuits

Patent metadata

Field	Value
Publication number	US-9865574-B2
Application number	US-201615143957-A
Country	US
Kind code	B2
Filing date	May 2, 2016
Priority date	Jun 19, 2013
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.

First claim

What is claimed is:

1. A package comprising:
a bottom package comprising:
a package substrate;
a device die over and bonded to the package substrate;
a molding material encapsulating at least a lower portion of the device die therein, wherein the molding material extends overlying the package substrate, wherein a top surface of the device die is exposed through the molding material;
a solder region at a top surface of, and electrically coupled to, the package substrate, wherein the solder region comprises a lower portion in the molding material, and an upper portion protruding out of, and higher than, a planar top surface the molding material; and
a first alignment mark at a top surface of the molding material, wherein an entirety of the first alignment mark is lower than the upper portion of the solder region; and

a top package bonded to the solder region, wherein first sidewalls of the lower portion of the solder region are smooth and rounded, and second sidewalls of the upper portion of the solder region are smooth and rounded, and wherein the first sidewalls are joined to the second sidewalls with a discontinuity in smoothness, and the discontinuity is at a level substantially coplanar with the planar top surface of the molding material, wherein the top package further comprises:
a second alignment mark extending from a top surface of the top package to an intermediate level of the top package;
an additional device die; and
an additional molding material encapsulating the additional device die, wherein the second alignment mark is formed in the additional molding material.

2. The package of claim 1 , wherein the upper portion has a rounded top surface.

3. The package of claim 1 , wherein the solder region is an edge solder region that is closest to an edge of the bottom package than all solder regions on the package substrate and at a same level as the edge solder region, and the first alignment mark is between the edge solder region and the edge of the bottom package.

4. The package of claim 1 further comprising a second alignment mark, wherein the second alignment mark further comprises an additional trench extending from the top surface of the device die into the device die.

5. The package of claim 4 , wherein the additional trench is located at a corner of the device die.

6. The package of claim 1 , wherein the first alignment mark comprises a trench extending from the top surface of the molding material into the molding material, and a top end of the first alignment mark is coplanar with the top surface of the device die.

7. A package comprising:
a package substrate;
a device die over and bonded to the package substrate;
a solder region physically joined to the package substrate, the solder region comprising:
a lower portion having first sidewalls, wherein the first sidewalls are smooth and rounded;
an upper portion comprising second sidewalls, wherein the second sidewalls are smooth and rounded, and wherein the first sidewalls and the second sidewalls are joined to each other with a discontinuity in smoothness;

a molding material molding the device die and the lower portion of the solder region therein, wherein the device die, the package substrate, and the molding material form a first package, wherein the upper portion of the solder region protrudes out of a planar top surface of the molding material, with a joint of the lower portion and the upper portion of the solder region being coplanar with the planar top surface of the molding material;
a first alignment mark extending into one of the device die and the molding material; and
a second package bonded to the first package through the solder region, wherein the second package comprises:
an additional device die;
an additional molding material encapsulating the additional device die; and
a second alignment mark, wherein the second alignment mark is formed in the additional molding material.

8. The package of claim 7 , wherein a top end of the first alignment mark is coplanar with the joint of the lower portion and the upper portion of the solder region.

9. The package of claim 7 , wherein the first alignment mark comprises a trench extending into the device die.

10. The package of claim 9 , wherein the trench of the first alignment mark is located at a corner of the device die.

11. The package of claim 7 , wherein the planar top surface of the molding material is coplanar with a top surface of the device die.

12. The package of claim 7 , wherein the first alignment mark is in the molding material, and the first alignment mark overlaps the device die.

13. The package of claim 7 , wherein the first alignment mark is in the device die, and a portion of the first alignment mark is at a same level as a portion of the molding material.

14. A package comprising:
a package substrate;
a device die over and bonded to the package substrate;
a solder region comprising:
bottom surface attached to the package substrate; and
a continuously rounded surface comprising rounded top surfaces and rounded sidewalls;

an encapsulating material encapsulating the device die therein, wherein the encapsulating material comprises a top portion overlapping the device die; and
an alignment mark comprising a trench extending into the top portion of the encapsulating material.

15. The package of claim 14 , wherein an entirety of the alignment mark is higher than the solder region.

16. The package of claim 14 , wherein the rounded top surfaces of the solder region have a spherical shape.

17. The package of claim 14 , wherein no package component is over and bonded to the solder region.

18. The package of claim 14 further comprising an additional alignment mark not overlapping the device die.

19. The package of claim 14 , wherein the encapsulating material comprises an opening, and an entirety of the solder region is in the opening.

20. The package of claim 14 , wherein the alignment mark is located at a corner of the package.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Kuei-Wei
• Lin Chih-Wei
• Lin Wei-Hung
• Cheng Ming-Da
• Liu Chung-Shi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title