Methods to control wafer warpage upon compression molding thereof and articles useful therefor

Patent metadata

Field	Value
Publication number	US-9865551-B2
Application number	US-201514953787-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Jul 22, 2013
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Provided herein are multilayer structures having a reduced propensity to warp upon curing of certain components thereof. In one aspect, there are provided multilayer assemblies comprising a plurality of the above-described multilayer structures. In another aspect, there are provided methods for reducing wafer warpage upon cure of molding compositions applied thereto. In yet another aspect, there are provided methods for preparing wafers having substantially no warpage upon cure thereof.

First claim

That which is claimed is:

1. A multilayer structure comprising:
a silicon layer containing a plurality of chips on one face thereof and an underfill layer underneath said chips,
a curable molding formulation applied to the same face as said plurality of chips, and
a reinforcing element applied to said curable molding formulation so as to minimize warping of said multilayer structure upon cure of said curable molding formulation,
wherein the coefficient of thermal expansion (CTE) of the silicon layer falls in the range of about 2-3 ppm/° C., and the CTE of the reinforcing element is +90% of the CTE of the silicon layer, and
wherein said curable molding formulation is characterized as:
being moldable within 30 minutes at a temperature in the range of 100° C. to 200° C.,
being curable within 8 hours at a temperature in the range of 100° C. to 175° C.

2. The structure of claim 1 wherein said reinforcing element is a ceramic thin plate or sheet.

3. The structure of claim 2 wherein said ceramic thin plate or sheet comprises silicon carbide, silicon nitride, alumina, alumina oxide, alumina-zirconia, aluminum-nitride, aluminum silicate, boron carbide, boron nitride, calcium aluminate, carbon, ceria, cordierite, forsterite, graphite, hafnia, hafnium oxide, kaolin, clay-based magnesia or magnesite, metal boride, mullite, rare earth oxides (REO), porcelain, sapphire, silica, fused silica, silicide, steatite, yttria, tungsten carbide, zircon, or zirconium phosphate.

4. The structure of claim 2 wherein said ceramic thin plate or sheet comprises silicon carbide, silicon nitride, boron carbide, boron nitride or tungsten carbide.

5. The structure of claim 1 wherein said curable molding formulation comprises a curable resin matrix containing 80-95 weight % filler.

6. The structure of claim 5 wherein said filler is silica, alumina, aluminum oxide, aluminum silicate, silicon nitride, aluminum nitride, silica-coated aluminum nitride, boron carbide, boron nitride, carbon black, or a combination of any two or more thereof.

7. The structure of claim 5 wherein said curable molding formulation is further characterized as:
having a CTE alpha 1<30 ppm/° C.,
having weight loss <1.0% at 250° C., and
having a Tg>50° C.

8. The structure of claim 7 wherein said curable molding formulation is a liquid compression molding formulation, a powder compression molding formulation, a compression molding film, or a panel molding formulation.

9. The structure of claim 7 wherein the article produced by curing undergoes at least 20% less warpage than an article prepared from a structure having no reinforcing element thereon.

10. The structure of claim 7 wherein an 8″ wafer of said structure undergoes <1 mm warpage upon cure and/or a 12″ wafer of said structure undergoes <2 mm warpage upon cure.

11. The structure of claim 1 wherein said silicon layer comprises one or more through silica vias (TSV).

12. A multilayer assembly comprising a plurality of structures according to claim 5 stacked so as to form a plurality of dies in a single stack.

13. The structure of claim 1 wherein said reinforcing element is a carbon fiber sheet, a thin glass sheet, a liquid crystal polymer (LCP) sheet, or a silicon plate or sheet.

14. A multilayer structure comprising:
a silicon layer containing a plurality of chips thereon and an underfill layer underneath said chips,
a cured molding formulation applied to the same face as said plurality of chips, and
a reinforcing element applied to said cured molding formulation so as to minimize warping of said multilayer structure upon cure of said cured molding formulation,
wherein the coefficient of thermal expansion (CTE) of the silicon layer falls in the range of about 2-3 ppm/° C., and the CTE of the reinforcing element is ±90% of the CTE of the silicon layer, and
wherein said cured molding formulation is characterized as:
being moldable within 30 minutes at a temperature in the range of 100° C. to 200° C., and
being curable within 8 hours at a temperature in the range of 100° C. to 175° C.

15. A method to reduce wafer warpage upon cure of a curable molding formulation applied to one side of a silicon support, said method comprising applying a reinforcing element to said curable molding formulation so as to minimize warping of said silicon support upon cure of said curable molding formulation prior to curing thereof, wherein the coefficient of thermal expansion (CTE) of the silicon support falls in the range of about 2-3 ppm/° C., and the CTE of the reinforcing element is ±90% of the CTE of the silicon support, and
wherein said curable molding formulation is characterized as:
being moldable within 30 minutes at a temperature in the range of 100° C. to 200° C.,
being curable within 8 hours at a temperature in the range of 100° C. to 175° C.

16. The method of claim 15 wherein wafer warpage upon cure is reduced by at least 20% relative to an article prepared from a structure having no reinforcing element thereon.

17. The method of claim 15 wherein an 8″ wafer of said structure undergoes <1 mm warpage upon cure and/or a 12″ wafer of said structure undergoes <2 mm warpage upon cure.

18. A method to prepare wafers having reduced warpage upon cure thereof, said method comprising:
applying a curable molding formulation to one side of a silicon layer, then applying a reinforcing element to said curable molding formulation so as to minimize warping of said wafer upon cure of said curable molding formulation, and
curing said curable molding formulation after application of said reinforcing element to said curable molding formulation,
wherein the coefficient of thermal expansion (CTE) of the silicon layer falls in the range of about 2-3 ppm/° C., and the CTE of the reinforcing element is ±90% of the CTE of the silicon layer, and
wherein said curable molding formulation is characterized as:
being moldable within 30 min minutes at a temperature in the range of 100° C. to 200° C.,
being curable within 8 hours at a temperature in the range of 100° C. to 175° C.

19. The method of claim 18 wherein an 8″ wafer of said structure undergoes <1 mm warpage upon cure and/or a 12″ wafer of said structure undergoes <2 mm warpage upon cure.

20. The method of claim 18 wherein wafer warpage upon cure is reduced by at least 20% relative to an article prepared from a structure having no reinforcing element thereon.

21. A multilayer structure comprising:
a silicon layer containing a plurality of chips on one face thereof and an underfill layer underneath said chips,
a curable molding formulation applied to the same face as said plurality of chips, and
a reinforcing element applied to said molding formulation so as to minimize warping of said multilayer structure upon cure of said molding formulation,
wherein the coefficient of thermal expansion (CTE) of the silicon layer falls in the range of about 2-3 ppm/° C., and the CTE of the reinforcing element is ±90% of the CTE of the silicon layer,
wherein said curable molding formulation comprises a curable resin matrix containing 80-95 weight % filler, and
wherein said curable molding formulation is characterized as:
being moldable within 30 minutes at a temperature in the range of 100° C. to 200° C.,
being curable within 8 hours at a temperature in the range of 100° C. to 175° C.,
having a CTE alpha 1<30 ppm/° C.,
having weight loss <1.0% at 250° C., and
having a Tg>50° C.

22. The structure of claim 21 wherein sai

Assignees

• Henkel IP & Holding GmbH

Inventors

• Takano Tadashi
• Hoang Gina

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/012

  of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/016

  using moulds · CPC title