Semiconductor device, manufacturing method thereof, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9865549-B2
Application number	US-201414505006-A
Country	US
Kind code	B2
Filing date	Oct 2, 2014
Priority date	Oct 9, 2013
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor substrate including:
a first plurality of wiring layers, each wiring layer of the first plurality of wiring layers including a wire, at least one low-dielectric rate interlayer insulating film layer, and a diffusion barrier film, wherein the first plurality of wiring layers is arranged such that at least one low-dielectric rate interlayer insulating film layer is between each of the wire and the diffusion barrier film and the diffusion barrier film is disposed on each wire of the first plurality of wiring layers;
a guard ring including a wire from each of the first plurality of wiring layers and a plurality of vias arranged in a stacked structure and in contact with a through electrode, wherein each wire from each of the first plurality of wiring layers is electrically connected to a respective via of the plurality of vias, and at least one via of the plurality of vias includes metal material disposed between the diffusion barrier film and the through electrode; and

a second semiconductor substrate including:
a second plurality of wiring layers, each wiring layer of the second plurality of wiring layers including a wire, at least one interlayer insulating film layer, and a diffusion barrier film, wherein the second plurality of wiring layers is arranged such that at least one interlayer insulating film layer is between each of the wire and the diffusion barrier film and each wire of the second plurality of wiring layers is disposed on the diffusion barrier film; and
a pad electrically connected to a wire of a wiring layer of the second plurality of wiring layers,

wherein the through electrode is buried inside the guard ring and electrically connected to the pad.

2. The semiconductor device according to claim 1 ,
wherein of the first and second semiconductor substrates are stacked, and
wherein the first semiconductor substrate is electrically connected to the second semiconductor substrate through the through electrode.

3. The semiconductor device according to claim 2 , wherein a semiconductor substrate including a contact image sensor (CIS) is stacked on the first semiconductor substrate.

4. The semiconductor device according to claim 2 , wherein the first semiconductor substrate includes a signal processing circuit.

5. The semiconductor device according to claim 2 , wherein the first semiconductor substrate includes a contact image sensor (CIS).

6. The semiconductor device according to claim 2 , wherein another semiconductor substrate includes a signal processing circuit.

7. The semiconductor device according to claim 2 , wherein a third semiconductor substrate includes a storage medium circuit.

8. The semiconductor device according to claim 1 , wherein the pad is located within an insulating film of the second semiconductor substrate.

9. An electronic apparatus comprising:
a semiconductor device, the semiconductor device including:
a first semiconductor substrate including:
a first plurality of wiring layers, each wiring layer of the first plurality of wiring layers including a wire, at least one low-dielectric rate interlayer insulating film layer, and a diffusion barrier film, wherein the first plurality of wiring layers is arranged such that at least one low-dielectric rate interlayer insulating film layer is between each of the wire and the diffusion barrier film and the diffusion barrier film is disposed on each wire of the first plurality of wiring layers;
a guard ring including a wire from each of the first plurality of wiring layers and a plurality of vias arranged in a stacked structure and in contact with a through electrode, wherein each wire from each of the first plurality of wiring layers is electrically connected to a respective via of the plurality of vias, and at least one via of the plurality of vias includes metal material disposed between the diffusion barrier film and the through electrode; and

a second semiconductor substrate including:
a second plurality of wiring layers, each wiring layer of the second plurality of wiring layers including a wire, at least one interlayer insulating film layer, and a diffusion barrier film, wherein the second plurality of wiring layers is arranged such that at least one interlayer insulating film layer is between each of the wire and the diffusion barrier film and each wire of the second plurality of wiring layers is disposed on the diffusion barrier film; and
a pad electrically connected to a wire of a wiring layer of the second plurality of wiring layers,

wherein the through electrode is buried inside the guard ring and electrically connected to the pad; and

a lens configured to direct light to an imaging surface of the semiconductor device.

10. The electronic apparatus according to claim 9 , wherein the semiconductor device is a solid-state imaging device, and wherein the semiconductor device further includes:
a signal processing circuit that processes an output signal that is output from the solid-state imaging device; and
an optical system that forms an image on an imaging plane of the solid-state imaging device.

11. The electronic apparatus according to claim 9 ,
wherein of the first and second semiconductor substrates are stacked, and
wherein the first semiconductor substrate is electrically connected to the second semiconductor substrate through the through electrode.

12. The electronic apparatus according to claim 11 , wherein the first semiconductor substrate includes a signal processing circuit.

13. The electronic apparatus according to claim 11 , wherein a third semiconductor substrate includes a storage medium circuit.

14. The semiconductor device according to claim 9 , wherein the pad is located within an insulating film of the second semiconductor substrate.

Assignees

• Sony Corp

Inventors

• Shigetoshi Takushi

Classifications

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title