Fault detection during operation of multiple applications at a mobile device

US9864857B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9864857-B2
Application numberUS-201313926460-A
CountryUS
Kind codeB2
Filing dateJun 25, 2013
Priority dateDec 15, 2009
Publication dateJan 9, 2018
Grant dateJan 9, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A particular method includes receiving authentication information at a device. The method also includes determining, by the device, whether a user is authenticated based on the authentication information. The method further includes executing, by the device, a first virtual machine in response to determining that the user is authenticated. The first virtual machine has access to sensitive information. The method also includes executing, by the device, a first application on the first virtual machine. The method further includes determining, by the device, whether execution of an instruction associated with a second virtual machine would result in a fault. The method also includes, in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction and allowing the second virtual machine to fail without adversely affecting the first virtual machine.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: receiving, at a device, first user input indicating selection of a first application of a first group of applications; in response to the first user input, executing, by the device, the first application on a first virtual machine associated with the first group; receiving, at the device during execution of the first application, second user input indicating selection of a second application of a second group of applications, the second group distinct from the first group; in response to the second user input, executing, by the device, the second application on a second virtual machine associated with the second group; intercepting, by a virtual machine monitor of the device, an instruction by the first virtual machine to access a computing resource, wherein the instruction is intercepted by the virtual machine monitor in response to the instruction corresponding to a privileged instruction that can be executed by a processor in a supervisory mode and cannot be executed by the processor in a user mode; determining, by the virtual machine monitor, whether execution of the instruction would result in a fault; and in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction. 2. The method of claim 1 , wherein the fault includes a memory access bounds fault, an input device access fault, an output device access fault, an invalid pointer fault, a stack overflow fault, or a combination thereof. 3. The method of claim 2 , wherein the virtual machine monitor does not intercept a second instruction by the second virtual machine in response to the second instruction corresponding to a non-privileged instruction that can be executed by the processor in the supervisory mode and in the user mode. 4. The method of claim 1 , further comprising: executing the first application on a first processor core of a plurality of processor cores; and executing the second application on a second processor core of the plurality of processor cores. 5. The method of claim 1 , wherein the second virtual machine is executed in response to determining that a user is authenticated based on received authentication information. 6. The method of claim 1 , wherein the first virtual machine includes a first virtual processor that implements a first instruction set architecture, wherein the second virtual machine includes a second virtual processor that implements a second instruction set architecture, and wherein the first instruction set architecture is different than the second instruction set architecture. 7. A device, comprising: a processor; and a computer-readable storage device storing instructions that, when executed by the processor, cause the processor to perform operations including: receiving first user input indicating selection of a first application of a first group of applications; in response to the first user input, executing the first application on a first virtual machine associated with the first group; receiving, during execution of the first application, second user input indicating selection of a second application of a second group of applications, the second group distinct from the first group; in response to the second user input, executing the second application on a second virtual machine associated with the second group; intercepting an instruction by the first virtual machine to access a computing resource, wherein the instruction is intercepted in response to the instruction corresponding to a privileged instruction that can be executed by the processor in a supervisory mode and cannot be executed by the processor in a user mode; determining whether execution of the instruction would result in a fault; and in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction. 8. The device of claim 7 , wherein the operations further comprise prompting for identification information before executing the first application. 9. The device of claim 8 , wherein the operations further comprise executing a virtual machine manager, wherein the virtual machine manager intercepts the instruction before execution by the first virtual machine and determines whether the instruction would result in the fault. 10. The device of claim 9 , wherein the virtual machine manager schedules execution of instructions by the first virtual machine and execution of second instructions by the second virtual machine in response to concurrent operation of the first virtual machine and the second virtual machine. 11. The device of claim 7 , wherein the processor includes a plurality of cores, wherein executing the first virtual machine is performed by a first core of the plurality of cores, and wherein executing the second virtual machine is performed by a second core of the plurality of cores. 12. The device of claim 8 , wherein the operations further include displaying a plurality of icons associated with a plurality of virtual machines to a display device. 13. The device of claim 7 , wherein the first virtual machine includes a first virtual processor that implements a first instruction set architecture, wherein the second virtual machine includes a second virtual processor that implements a second instruction set architecture, and wherein the first instruction set architecture is different than the second instruction set architecture. 14. A computer-readable hardware storage device storing instructions that, when executed by a processor, cause the processor to perform operations comprising: receiving first user input indicating selection of a first application of a first group of applications; in response to the first user input, executing the first application on a first virtual machine associated with the first group; receiving, during execution of the first application, second user input indicating selection of a second application of a second group of applications, the second group distinct from the first group; in response to the second user input, executing the second application on a second virtual machine associated with the second group; intercepting an instruction by the first virtual machine to access a computing resource, wherein the instruction is intercepted in response to the instruction corresponding to a privileged instruction that can be executed by the processor in a supervisory mode and cannot be executed by the processor in a user mode; determining whether execution of the instruction would result in a fault; and in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction. 15. The computer-readable hardware storage device of claim 14 , wherein the operations further comprise, prior to determining whether execution of the instruction would result in the fault, displaying, on a display, a plurality of icons associated with a plurality of virtual machines, wherein the plurality of virtual machines includes the first virtual machine and the second virtual machine. 16. The computer-readable hardware storage device of claim 14 , wherein the operations further comprise, prior to determining whether execution of the instruction would result in the fault, prompting for authentication information in response to the first user input. 17. The computer-readable hardware storage device of claim 14 , wherein the operations further comprise: executing a first plurality of applications on a first processor core of a plurality of

Assignees

Inventors

Classifications

  • using a touch-screen or digitiser, e.g. input of commands through traced gestures · CPC title

  • by electronic means · CPC title

  • Electricity · mapped topic

  • using an additional device, e.g. smartcard, SIM or a different communication terminal (cryptographic mechanisms or cryptographic arrangements for entity authentication involving additional secure or trusted devices H04L9/3234) · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9864857B2 cover?
A particular method includes receiving authentication information at a device. The method also includes determining, by the device, whether a user is authenticated based on the authentication information. The method further includes executing, by the device, a first virtual machine in response to determining that the user is authenticated. The first virtual machine has access to sensitive infor…
Who is the assignee on this patent?
At & T Mobility Ii Llc, AT&T Mobility II LC
What technology area does this patent fall under?
Primary CPC classification G06F21/53. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).