Automatic generation of physically aware aggregation/distribution networks

Patent metadata

Field	Value
Publication number	US-9864728-B2
Application number	US-201514726289-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Aspects of the present disclosure provide systems and methods for automatic generation of physically aware aggregation/distribution networks that enable optimized arrangement of a plurality of hardware elements, and provide positions and connectivity for one or more intermediate hardware elements. One or more intermediate hardware elements can be configured to aggregate signals/commands/messages/data from their corresponding hardware elements or from other intermediate hardware elements, and send the aggregated signals/commands/messages/data to a root hardware element that acts as a communication interface for the network. The intermediate hardware elements can also be configured to segregate/distribute signals/commands/message received from the root hardware element to a plurality of specified hardware elements and/or intermediate hardware elements.

First claim

What is claimed is:

1. A method, comprising:
generating an arrangement of a plurality of hardware elements and a root hardware element from processing an input specification; and

providing, using a computer, positions and connectivity for one or more intermediate hardware elements configured to:
aggregate signals from the plurality of hardware elements to the root hardware element; or
distribute signals to the plurality of hardware elements from the root hardware element, and
providing paths between the one or more intermediate hardware elements, the plurality of hardware elements and the root hardware element based on the positions and connectivity.

2. The method of claim 1 , wherein the providing the positions and the connectivity for the one or more intermediate hardware elements is based on at least one of:
minimum distance from a hardware element and associated intermediate element;
specified permitted number of intermediate hardware elements; and
disallowed regions for the intermediate elements.

3. The method of claim 1 , further comprising utilizing a routing function to determine connectivity topology between the intermediate hardware elements.

4. The method of claim 1 , wherein the providing the positions for the one or more intermediate hardware elements is based on permitted positioning of Network on Chip (NoC) elements, and wherein the providing the connectivity for the one or more intermediate hardware elements is based on permitted positioning of NoC channels.

5. The method of claim 1 , wherein the one or more intermediate hardware elements are configured to aggregate signals from the plurality of hardware elements to the root hardware element by at least one of:
aggregating interrupt signals from the plurality of hardware elements into a single output interrupt signal to the root hardware element through an aggregation function;
aggregating reset done signals from the plurality of hardware elements into a single output reset done signal to the root hardware element through the aggregation function;
aggregating reset started signals from the plurality of hardware elements into a single output reset started signal to the root hardware element through the aggregation function;
aggregating power management control signals from the plurality of hardware elements into a single output power management control signal to the root hardware element through the aggregation function.

6. The method of claim 1 , wherein the one or more intermediate hardware elements are configured to distribute signals to the plurality of hardware elements from the root hardware element by identifying a destination of the signals through at least one of a one hot encoding format, an M-Hot encoding format, a binary format, and a tree structure format.

7. The method of claim 1 , wherein the plurality of hardware elements and the root hardware element are configured according to a time domain multiplexing schedule to facilitate:
distribution of the signals to one of the plurality of hardware elements from the root hardware element based on the time domain multiplexing schedule; and

source identification to aggregate signals from the plurality of hardware elements to the root hardware element, wherein the root hardware element is configured to conduct source identification based on the time domain multiplexing schedule.

8. The method of claim 1 , wherein the one or more intermediate hardware elements are configured to distribute signals to the plurality of hardware elements from the root hardware element by at least one of:
distributing a reset distribution signal from the root hardware element to the plurality of hardware elements;
distributing a power management control signal from the root hardware element to the plurality of hardware elements.

9. The method of claim 1 , wherein each of the one or more intermediate hardware elements are configured with a clock based on a clock domain associated with the position of the each of the one or more intermediate hardware elements.

10. A non-transitory computer readable medium storing instructions for executing a process, the instructions comprising:
generating an arrangement of a plurality of hardware elements and a root hardware element from processing an input specification; and

providing positions and connectivity for one or more intermediate hardware elements configured to:
aggregate signals from the plurality of hardware elements to the root hardware element; or
distribute signals to the plurality of hardware elements from the root hardware element; and
providing paths between the one or more intermediate hardware elements, the plurality of hardware elements and the root hardware element based on the positions and connectivity.

11. The non-transitory computer readable medium of claim 10 , wherein the providing the positions and the connectivity for the one or more intermediate hardware elements is based on at least one of:
minimum distance from a hardware element and associated intermediate element;
specified permitted number of intermediate hardware elements; and
disallowed regions for the intermediate elements.

12. The non-transitory computer readable medium of claim 10 , wherein the instructions further comprise utilizing a routing function to determine connectivity topology between the intermediate hardware elements.

13. The non-transitory computer readable medium of claim 10 , wherein the providing the positions for the one or more intermediate hardware elements is based on permitted positioning of Network on Chip (NoC) elements, and wherein the providing the connectivity for the one or more intermediate hardware elements is based on permitted positioning of NoC channels.

14. The non-transitory computer readable medium of claim 10 , wherein the one or more intermediate hardware elements are configured to aggregate signals from the plurality of hardware elements to the root hardware element by at least one of:
aggregating interrupt signals from the plurality of hardware elements into a single output interrupt signal to the root hardware element through an aggregation function;
aggregating reset done signals from the plurality of hardware elements into a single output reset done signal to the root hardware element through the aggregation function;
aggregating reset started signals from the plurality of hardware elements into a single output reset started signal to the root hardware element through the aggregation function;
aggregating power management control signals from the plurality of hardware elements into a single output power management control signal to the root hardware element through the aggregation function.

15. The non-transitory computer readable medium of claim 10 , wherein the one or more intermediate hardware elements are configured to distribute signals to the plurality of hardware elements from the root hardware element by identifying a destination of the signals through at least one of a one hot encoding format, an M-Hot encoding format, a binary format, and a tree structure format.

16. The non-transitory computer readable medium of claim 10 , wherein the plurality of hardware elements and the root hardware element are configured according to a time domain multiplexing schedule to facilitate:
distribution of the signals to one of the plurality of hardware elements from the root hardware element based on the time domain multiplexing schedule; and
source identification to aggregate signals from the plurality of hardware elements to the root hardware element, wherein the roo

Assignees

• Netspeed Systems
• Netspeed Systems Inc

Inventors

• Norige Eric
• Kumar Sailesh

Classifications

• H04L49/109

  Integrated on microchip, e.g. switch-on-chip · CPC title

• G06F15/7825 Primary

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title