System and method for communication between a data-acquisition circuit and a data-processing circuit

Patent metadata

Field	Value
Publication number	US-9864722-B2
Application number	US-201214367734-A
Country	US
Kind code	B2
Filing date	Dec 14, 2012
Priority date	Dec 20, 2011
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A communication system coupled to a data-acquisition circuit and to a data-processing circuit is provided, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in the shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. Methods for communication between a data-acquisition circuit and a data-processing circuit are also provided.

First claim

The invention claimed is:

1. A communication system for operating between a data-acquisition circuit and a data-processing circuit, the data acquisition circuit configured to generate data-words having a predefined number of data-bits to be written and to be read, the communication system comprising:
at least one shift register having a serial input for receiving data-words and storing in series the predefined number of data-bits to be written, and a serial output for outputting data-bits in series, whereby said at least one shift register further includes a plurality of parallel outputs for, simultaneously to the serial storing and serial outputting, outputting of data-bits stored in said at least one shift register;
an addressing circuit coupled to said at least one shift register for identifying the positions of each data-bit of each data-word stored in said at least one shift register and for calculating the address of a data-word to be selected; and
a multiplexer coupled to the plurality of parallel outputs of said at least one shift register for reading out under a control of the addressing circuit, a predefined number of data-bits of the selected data-word, and for serially transmitting the data-word to the data-processing circuit.

2. The communication system as claimed in claim 1 , wherein said at least one shift register comprises a plurality of storage components connected in series for storing data-bits in series, and a plurality of addressing circuits and multiplexors for outputting several data-words from the parallel outputs.

3. The communication system as claimed in claim 1 , further comprising means for coupling operatively a plurality of shift registers in at least one register column, whereby each column comprises:
a plurality (j) of shift registers, wherein the serial output of one register (j−1) constitutes the serial input of the following register (j);
identification means coupled to said at least one column of registers (j) for identifying the positions of data-bits written in the plurality of shift registers; and
a multiplexer coupled to said at least one register column for outputting to the processing circuit data originating from the parallel outputs of the shift registers (j).

4. The communication system as claimed in claim 3 , further comprising means for the operatively combining a plurality of shift register columns in a storage matrix of capacity equal to that of the acquisition circuit.

5. The communication system as claimed in claim 1 , further comprising:
a selector circuit coupled to said at least one shift register for selecting data-bits in series received as input from said at least one shift register, either from the acquisition circuit, from one or more adjoining shift registers, or from the processing circuit.

6. The communication system as claimed in claim 5 , further comprising:
a configuration circuit coupled to the selector circuit for configuring the number of data-bits in series received from the acquisition circuit, from one or more adjoining shift registers, or from the processing circuit.

7. The communication system as claimed in claim 6 , wherein the adjoining shift registers are in one or more register columns.

8. The communication system as claimed in claim 1 , wherein the data-processing circuit comprises a plurality of processing units, whereby each processing unit is coupled to said at least one shift register for receiving data-bits from the serial output of said at least one shift register and/or data-bits from parallel outputs.

9. The communication system as claimed in claim 1 , wherein the data-acquisition circuit comprises a pixel matrix structured in lines and columns, and a control circuit for reading the pixel matrix in rolling-shutter mode, and for serially outputting pixel values to the communication system.

10. The communication system as claimed in claim 1 , wherein the acquisition circuit is a stacked type integrated vision system, and in which the data-processing circuit is a “Single Instruction Multiple Data” type processor.

11. The communication system as claimed in claim 1 , wherein said at least one shift register column is a Random Access Memory.

12. A communication method for operating between a data-acquisition circuit and a data-processing circuit, the data acquisition circuit configured to generate data-words having a predefined number of data-bits to be written and to be read, the method comprising the steps of:
a) defining a number of writing operations and initializing a position counter;
b) detecting a data writing request;
c) writing and storing a first data-bit in a first storage component of a shift register, wherein said shift register comprises a serial input for receiving data-bits in series from the data-acquisition circuit and a serial output for outputting data-bits in series, and further comprising parallel outputs associated with each storage component in said register, for, simultaneously to the serial storing and serial outputting, outputting data-bits stored in said storage components;
d) identifying the position of each data-bit of each data-word stored in the shift register;
e) incrementing the position counter,
f) repeating steps b) to e) for the number of writing operations defined;
g) detecting a data-word readout request;
h) calculating the address of the data-word stored in the shift register from the positions of the data-bits identified at step (d);
i) reading out, from the parallel outputs, data-bits stored in the shift register at the address calculated; and
j) multiplexing the data-bits read out for transmitting data-bits in series to the data-processing circuit.

13. The method as claimed in claim 12 , wherein the writing step (c) and the readout step (i) are asynchronous.

14. The method as claimed in claim 12 , wherein the writing step (c) comprises writing of data-bits from the data-processing circuit.

Assignees

• Commissariat Energie Atomique

Inventors

• Chevobbe Stephane
• Duranton Marc

Classifications

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4009

  with data restructuring · CPC title