Circuit that selects EPROMs individually and in parallel

Patent metadata

Field	Value
Publication number	US-9864524-B2
Application number	US-201715416813-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	Sep 27, 2011
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.

First claim

The invention claimed is:

1. A method comprising:
providing a first EPROM and a second EPROM;
selecting one of the first EPROM, the second EPROM, and a parallel combination of the first EPROM and the second EPROM; and
measuring a resistance through the selected one of the first EPROM, the second EPROM, and the parallel combination of the first EPROM and the second EPROM, wherein when the parallel combination of the first EPROM and the second EPROM is selected, the measured resistance is of a parallel resistance of the first EPROM and the second EPROM.

2. The method of claim 1 , comprising:
setting the first EPROM to one of a first un-programmed resistance and a first programmed resistance; and
setting the second EPROM to one of a second un-programmed resistance and a second programmed resistance, wherein each resistance of the first un-programmed resistance, the first programmed resistance, the second un-programmed resistance, and the second programmed resistance is different than each of the other three resistances.

3. The method of claim 1 , comprising:
providing a third EPROM;
selecting one of the first EPROM, the second EPROM, the third EPROM, and each parallel combination of two or more of the first EPROM and the second EPROM and the third EPROM; and
measuring a resistance through the selected one of the first EPROM, the second EPROM, the third EPROM, and each parallel combination of two or more of the first EPROM and the second EPROM and the third EPROM.

4. The method of claim 1 , wherein the first EPROM and second EPROM are connected to a common node when both the first EPROM and the second EPROM are selected to select the parallel combination of the first EPROM and second EPROM.

5. The method of claim 4 , further comprising:
selecting both the first EPROM and the second EPROM to select the parallel combination of the first EPROM and the second EPROM by activating select signals to gates of respective select transistors that connect the first and second EPROMs to the common node.

6. The method of claim 4 , further comprising:
activating a bit address transistor that connects the common node to a reference potential, wherein the parallel resistance of the first EPROM and the second EPROM is measured based on current flow through the first EPROM and the second EPROM and through the bit address transistor.

7. The method of claim 6 , wherein activating the bit address transistor is based on a bit address signal provided to a gate of the bit address transistor.

8. The method of claim 1 , wherein when the first EPROM is selected but the second EPROM is not selected, the measured resistance is of a resistance of the first EPROM.

9. The method of claim 8 , wherein when the second EPROM is selected but the first EPROM is not selected, the measured resistance is of a resistance of the second EPROM.

10. The method of claim 1 , wherein the first EPROM is settable to a first state and a second state, the second EPROM is settable to a third state and a fourth state, and the parallel combination of the first EPROM and the second EPROM is settable to a fifth state and a sixth state.

11. The method of claim 10 , wherein the first EPROM and the second EPROM form an EPROM bit that is settable to any of the first state, the second state, the third state, the fourth state, the fifth state, and the sixth state based on activating a bit address transistor that is controlled by a bit address signal.

12. The method of claim 10 , wherein the first state is represented by a first resistance value, the second state is represented by a second resistance value, the third state is represented by a third resistance value, the fourth state is represented by a fourth resistance value, the fifth state is represented by a fifth resistance value, and the sixth state is represented by a sixth resistance value.

13. The method of claim 1 , wherein the first EPROM is a first type of EPROM, and the second EPROM is a second type of EPROM different from the first type of EPROM.

14. The method of claim 1 , wherein the first EPROM and the second EPROM are part of a printhead.

15. A method comprising:
connecting a first EPROM cell between a voltage line and a common node;
connecting a second EPROM cell between the voltage line and the common node;
connecting the common node through a bit address transistor to a reference potential, wherein selection of both the first EPROM cell and the second EPROM cell provides a parallel combination of the first EPROM cell and the second EPROM cell that is connected through the bit address transistor to the reference potential.

16. The method of claim 15 , further comprising:
connecting a first transistor between the first EPROM cell and the common node, a gate of the first transistor connected to a first select signal; and
connecting a second transistor between the second EPROM cell and the common node, a gate of the second transistor connected to a second select signal.

17. The method of claim 15 , wherein the first EPROM cell when selected provides a first resistance, the second EPROM cell when selected provides a second resistance different from the first resistance, and the parallel combination of the first EPROM cell and the second EPROM cell provides a parallel resistance different from each of the first resistance and the second resistance.

18. The method of claim 15 , wherein the first EPROM cell and the second EPROM cell are part of a memory bit.

19. The method of claim 15 , wherein the first EPROM cell and the second EPROM cell are part of a printhead.

Assignees

• Hewlett Packard Development Co Lp

Inventors

• Ge Ning
• Mikulan Paul I
• Peh Bee Ling

Classifications

• B41J2/04586

  controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• B41J2/04541

  Specific driving circuit · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title