Protective layering process for circuit boards

Patent metadata

Field	Value
Publication number	US-9860992-B1
Application number	US-201514963920-A
Country	US
Kind code	B1
Filing date	Dec 9, 2015
Priority date	Nov 28, 2011
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A polymer layering process that encapsulates and protects electronics components with complex and imprecise geometries. The protective layering process provides a combination of a flexible mold and/or a rigid mold that apply close-forming, encapsulating the polymer layers to the electronic components and precision assemblies. Polymer layer protective jackets are shaped to as-populated circuit boards and assemblies, providing tightly fit barriers with fine resolution accommodating imprecise geometries. The protective jackets can be formed in rigid, semi-rigid, or highly flexible polymer films, to protect the circuitry from the elements, CTE mismatches, shock and vibration loads and extreme g-forces.

First claim

What is claimed is:

1. A method for encapsulating a populated circuit board assembly having an imprecise geometry, with at least one protective layer that is tightly fit to the imprecise geometry of the populated circuit board assembly, the method comprising:
making a mold of the populated circuit board assembly;
using the mold to encapsulate the populated circuit board assembly with said at least one protective layer;
wherein making the mold includes:
scanning the populated circuit board assembly to create a surface file of the populated circuit board assembly;
enlarging the surface file to accommodate for variations of the mold and said at least one protective layer;
using the enlarged surface file to create a positive mold;

wherein encapsulating the populated circuit board assembly with said at least one protective layer includes:
heating a first protective layer of said at least one protective layer;
drawing the heated first protective layer over and past the positive mold, in order to form an envelope with a substantially precise representation of the populated circuit board assembly;
releasing the envelope from the positive mold; and
placing the formed envelope onto the populated circuit board assembly to be encapsulated.

2. The method according to claim 1 , wherein the variations of the mold and said at least one protective layer include shrinkage of the positive mold and thicknesses of said at least one protective layer.

3. The method according to claim 1 , wherein the positive mold has a metallic composition.

4. The method according to claim 3 , wherein the positive mold is made of aluminum.

5. The method according to claim 1 , wherein making the mold further includes drilling vacuum holes in the positive mold.

6. The method according to claim 5 , wherein encapsulating the populated circuit board assembly further includes applying vacuum through the vacuum holes to draw the first protective layer onto the positive mold.

7. The method according to claim 1 , wherein encapsulating the populated circuit board assembly further includes heating the positive mold prior to drawing the first protective layer over and past the positive mold.

8. The method according to claim 1 , further comprising repeating the steps of encapsulating populated circuit board assembly for each additional protective layer.

9. The method according to claim 1 , wherein said at least one protective layer includes a polymer layer.

10. The method according to claim 1 , wherein said at least one protective layer comprises multiple successively superimposed layers that include any one or more of: a thermally conductive layer, an electromagnetic shielding layer, an impact protection layer, and an environmental protection layer.

Assignees

• Us Army

Inventors

• Chao Nien-Hua
• Dispenza John A
• Deangelis Mario

Classifications

• H10W74/016

  using moulds · CPC title

• H05K3/0014 Primary

  Shaping of the substrate, e.g. by moulding · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K2203/1316

  Moulded encapsulation of mounted components · CPC title

• H05K3/0047

  Drilling of holes · CPC title