Circuit board structure and manufacturing method thereof

US9860984B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9860984-B2
Application numberUS-201615287718-A
CountryUS
Kind codeB2
Filing dateOct 6, 2016
Priority dateDec 14, 2015
Publication dateJan 2, 2018
Grant dateJan 2, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.

First claim

Opening claim text (preview).

What is claimed is: 1. A manufacturing method of a circuit board structure, comprising: providing an inner circuit structure, the inner circuit structure comprises a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first patterned circuit layer and the second patterned circuit layer; forming a metal pillar on a pad of the first patterned circuit layer; performing a build-up process, to press a first build-up circuit structure on the first patterned circuit layer, wherein the first build-up circuit structure at least comprises an inner dielectric layer, and the inner dielectric layer directly covers the upper surface of the core layer and the first patterned circuit layer; using a contact distance detector to detect an upper surface of the metal pillar relatively far away from the first patterned circuit layer; and using the upper surface of the metal pillar to serve as a depth reference surface, performing a hole drilling process on the first build-up circuit structure, to remove a portion of the first build-up circuit structure and the whole metal pillar, or remove a portion of the first build-up circuit structure and a portion of the metal pillar, so as to form a cavity extending from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion of the inner dielectric, wherein the cavity exposes an inner surface of the inner dielectric layer, and the inner dielectric layer has an opening connecting to the cavity, the pad is located in the opening, and a hole diameter of the opening is smaller than a hole diameter of the cavity, and an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference. 2. The manufacturing method of the circuit board structure as recited in claim 1 , wherein the contact distance detector is a probe device. 3. The manufacturing method of the circuit board structure as recited in claim 1 , wherein edges of the metal pillar and edges of the pad are coplanar. 4. The manufacturing method of the circuit board structure as recited in claim 3 , further comprising: pressing a second build-up circuit structure on the second patterned circuit layer simultaneously when performing the build-up process; after removing the portion of the first build-up circuit structure and the portion of the metal pillar, a remaining metal pillar is located inside the opening, and an upper surface of the metal pillar and the inner surface of the inner dielectric layer are coplanar; forming a first patterned solder mask layer on a first surface of the first build-up circuit structure relatively far away from the inner circuit structure and on the inner surface of the inner dielectric layer, wherein the first patterned solder mask layer exposes the upper surface of the metal pillar; and forming a second patterned solder mask layer on a second surface of the second build-up circuit structure relatively far away from the inner circuit structure. 5. The manufacturing method of the circuit board structure as recited in claim 4 , wherein after removing the portion of the first build-up circuit structure and the portion of the metal pillar, a height of the remaining metal pillar is equal to 5% to 50% of a height of the original metal pillar. 6. The manufacturing method of the circuit board structure as recited in claim 4 , wherein the first build-up circuit structure further comprises at least a first dielectric layer, at least a first patterned conductive layer and at least a first conductive through hole structure penetrating through the first dielectric layer and the inner dielectric layer, the first patterned conductive layer and the first dielectric layer are sequentially stacked on the inner dielectric layer, and the first patterned conductive layer is electrically connected to the first patterned circuit layer via the first conductive through hole structure, and the second build-up circuit structure comprises at least a second dielectric layer, at least a second patterned conductive layer and at least a second conductive through hole structure penetrating through the second dielectric layer, the second dielectric layer and the second patterned conductive layer are sequentially stacked on the lower surface of the core layer, and the second patterned conductive layer is electrically connected to the second patterned circuit layer via the second conductive through hole structure. 7. The manufacturing method of the circuit board structure as recited in claim 3 , further comprising: pressing a second build-up circuit structure on the second patterned circuit layer simultaneously when performing the build-up process; forming a first patterned solder mask layer on a first surface of the first build-up circuit structure relatively far away from the inner circuit structure before performing the hole drilling process on the first build-up circuit structure; and forming a second patterned solder mask layer on a second surface of the second build-up circuit structure relatively far away from the inner circuit structure before performing the hole drilling process on the first build-up circuit structure. 8. The manufacturing method of the circuit board structure as recited in claim 7 , wherein the first build-up circuit structure further comprises at least a first dielectric layer, at least a first patterned conductive layer and at least a first conductive through hole structure penetrating through the first dielectric layer and the inner dielectric layer, the first patterned conductive layer and the first dielectric layer are sequentially stacked on the inner dielectric layer, and the first patterned conductive layer is electrically connected to the first patterned circuit layer via the first conductive through hole structure, and the second build-up circuit structure comprises at least a second dielectric layer, at least a second patterned conductive layer and at least a second conductive through hole structure penetrating through the second dielectric layer, the second dielectric layer and the second patterned conductive layer are sequentially stacked on the lower surface of the core layer, and the second patterned conductive layer is electrically connected to the second patterned circuit layer via the second conductive through hole structure. 9. The manufacturing method of the circuit board structure as recited in claim 1 , wherein edges of the metal pillar are shrunk from edges of the pad. 10. The manufacturing method of the circuit board structure as recited in claim 9 , wherein after removing the portion of the first build-up circuit structure and the whole metal pillar, the inner dielectric layer covers a portion of the top surface of the pad. 11. The manufacturing method of the circuit board structure as recited in claim 1 , wherein edges of the metal pillar are protruded from edges of the pad. 12. The manufacturing method of the circuit board structure as recited in claim 11 , wherein after removing the portion of the first build-up circuit structure and the whole metal pillar, the inner surface of the inner dielectric layer comprises a first inner surface and a second inner surface, the first inner surface is higher than the second inner surface, and the second inner surface and the top surface of the pad are coplanar.

Assignees

Inventors

Classifications

  • by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

  • Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads · CPC title

  • H05K1/111Primary

    Pads for surface mounting, e.g. lay-out · CPC title

  • Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence) · CPC title

  • Metal filled via · CPC title

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Frequently asked questions

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What does patent US9860984B2 cover?
A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterne…
Who is the assignee on this patent?
Unimicron Technology Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/111. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 02 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).