Solid-state imaging device

Patent metadata

Field	Value
Publication number	US-9860471-B2
Application number	US-201514925333-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Apr 18, 2003
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A CMOS sensor has unit pixels each structured by a light receiving element and three transistors, to prevent against the phenomenon of saturation shading and the reduction of dynamic range. The transition time (fall time), in switching off the voltage on a drain line shared in all pixels, is given longer than the transition time in turning of any of the reset line and the transfer line. For this reason, the transistor constituting a DRN drive buffer is made proper in its W/L ratio. Meanwhile, a control resistance or current source is inserted on a line to the GND, to make proper the operation current during driving. This reduces saturation shading amount. By making a reset transistor in a depression type, the leak current to a floating diffusion is suppressed to broaden the dynamic range.

First claim

What is claimed is:

1. An imaging device comprising:
a plurality of pixels; and
a driving circuit configured to drive the plurality of pixels,
wherein at least one of the plurality of pixels includes:
a photodiode;
a floating diffusion;
a transfer transistor connected between the photodiode and the floating diffusion;
a reset transistor connected between the floating diffusion and a drain line; and
an amplifier transistor, a gate of the amplifier transistor connected to the floating diffusion,

wherein the driving circuit includes a transistor connected to the drain line, and
wherein a W/L ratio (W is a gate width, L is a gate length) of the transistor connected to the drain line is in a range of 1/0.6 to 1/20.

2. An imaging device according to claim 1 , wherein an off transition time on the drain line is a half of a pixel clock period or greater.

3. An imaging device according to claim 1 , wherein a transfer drive buffer includes a transistor connected at least to the transfer line, a reset drive buffer includes a transistor connected at least to the reset line, and wherein the transistor connected to the drain line has a W/L ratio set in a range of 1/5 times to 1/2500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line.

4. An imaging device according to claim 3 , wherein the transistor connected to the drain line has a W/L ratio set in a range of 1/10 times to 1/500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line.

5. An imaging device according to claim 1 , further comprising a resistance element for limiting a drive current provided between an off-side reference line of a drain drive buffer and a reference power source regulating an off voltage to the drain line.

6. An imaging device according to claim 1 , further comprising a current source for regulating a drive current provided between an off-side reference line of a drain drive buffer and a reference power source regulating an off voltage to the drain line.

7. An imaging device comprising:
a plurality of pixels; and
a driving circuit configured to drive the plurality of pixels,
wherein at least one of the plurality of pixels includes:
a photodiode;
a floating diffusion;
a transfer transistor connected between the photodiode and the floating diffusion;
a reset transistor connected between the floating diffusion and a drain line; and
an amplifier transistor, a gate of the amplifier transistor connected to the floating diffusion,

wherein the driving circuit includes a transistor connected to the drain line, and
wherein a W/L ratio (W is a gate width, L is a gate length) of the transistor connected to the drain line is in a range of 1/1 to 1/20.

8. An imaging device according to claim 7 , wherein an off transition time on the drain line is a half of a pixel clock period or greater.

9. An imaging device according to claim 7 , wherein a transfer drive buffer includes a transistor connected at least to the transfer line, a reset drive buffer includes a transistor connected at least to the reset line, and wherein the transistor connected to the drain line has a W/L ratio set in a range of 1/5 times to 1/2500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line.

10. An imaging device according to claim 9 , wherein the transistor connected to the drain line has a W/L ratio set in a range of 1/10 times to 1/500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line.

11. An imaging device according to claim 7 , further comprising a resistance element for limiting a drive current provided between an off-side reference line of a drain drive buffer and a reference power source regulating an off voltage to the drain line.

12. An imaging device according to claim 7 , further comprising a current source for regulating a drive current provided between an off-side reference line of a drain drive buffer and a reference power source regulating an off voltage to the drain line.

13. An imaging device comprising: a plurality of pixels; and a driving circuit configured to drive the plurality of pixels, wherein at least one of the plurality of pixels includes: a photodiode; a floating diffusion; a transfer transistor connected between the photodiode and the floating diffusion; a reset transistor connected between the floating diffusion and a drain line; and an amplifier transistor, a gate of the amplifier transistor connected to the floating diffusion, wherein the driving circuit includes a transistor connected to the drain line, and wherein a W/L ratio (W is a gate width, L is a gate length) of the transistor connected to the drain line is in a range of 500/0.6 to 2/0.6.

14. An imaging device according to claim 13 , wherein an off transition time on the drain line is a half of a pixel clock period or greater.

15. An imaging device according to claim 13 , wherein a transfer drive buffer includes a transistor connected at least to the transfer line, a reset drive buffer includes a transistor connected at least to the reset line, and wherein the transistor connected to the drain line has a W/L ratio set in a range of 1/5 times to 1/2500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line.

16. An imaging device according to claim 15 , wherein the transistor connected to the drain line has a W/L ratio set in a range of 1/10 times to 1/500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line.

17. An imaging device according to claim 13 , further comprising a resistance element for limiting a drive current provided between an off-side reference line of a drain drive buffer and a reference power source regulating an off voltage to the drain line.

18. An imaging device according to claim 13 , further comprising a current source for regulating a drive current provided between an off-side reference line of a drain drive buffer and a reference power source regulating an off voltage to the drain line.

Assignees

• Sony Corp

Inventors

• Mabuchi Keiji
• Funatsu Eiichi
• Masanori Kasai

Classifications

• H04N25/709 Primary

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• A47J19/06 Primary

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• H04N23/54

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