Image sensor having different substrate bias voltages

Patent metadata

Field	Value
Publication number	US-9860467-B2
Application number	US-201614989055-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Feb 25, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

An image sensor having different bias voltages is provided. The image sensor may include a plurality of pixels configured to output pixel signals based on a received optical signal, and logic circuits configured to output the pixels signals as image data. The pixels may be formed on a first region of a semiconductor substrate, the first region being substrate biased to a first voltage. The logic circuits may be formed on a second region of the semiconductor substrate different from the first region, the second region being substrate biased to a second voltage different from the first voltage. A full-well capacitance (FWC) of the photodiode may be increased by applying the first voltage, which is a negative (−) voltage, to a photodiode of a pixel to reduce (or, alternatively prevent) a blooming effect.

First claim

What is claimed is:

1. An image sensor comprising:
a plurality of pixels on a first region of a semiconductor substrate, the plurality of pixels configured to output pixel signals based on a received optical signal; and
logic circuits on a second region of the semiconductor substrate, the second region being a different region from the first region, the logic circuits configured to output the pixel signals as image data, wherein,
the first region is substrate biased to a first voltage and the second region is substrate biased to a second voltage different from the first voltage, and

the first voltage is a negative voltage.

2. The image sensor of claim 1 , wherein the second voltage is a ground voltage.

3. The image sensor of claim 1 , wherein each of the plurality of pixels comprises:
a photodiode configured to output a photocharge based on the optical signal, the photodiode including a first impurity area having a first conductive type impurity and a second impurity area having a second conductive type impurity, the second impurity area surrounding the first impurity area, the second impurity area of the photodiode being in the first region of the semiconductor substrate and the second impurity area having the first voltage applied thereto,
a sensing node adjacent to the photodiode, the sensing node configured to sense the photocharge, and
a driver configured to output the sensed photocharge as the pixel signals.

4. The image sensor of claim 3 , wherein the first impurity area is an n-type impurity area and the second impurity area is a p-type impurity area.

5. The image sensor of claim 3 , wherein each of the plurality of pixels further comprises:
a transfer transistor between the photodiode and the sensing node, the transfer transistor configured to transfer the photocharge to the sensing node based on a transfer control signal.

6. The image sensor of claim 5 , wherein each of the plurality of pixels further comprises:
a reset transistor between a power voltage and the sensing node, the reset transistor configured to reset the sensing node to the power voltage based on a reset control signal, the transfer transistor and the reset transistor being commonly connected to the sensing node.

7. The image sensor of claim 3 , wherein the driver comprises:
a drive transistor configured to output a signal based on a voltage level of the sensing node, the drive transistor including a source having a power voltage applied thereto.

8. The image sensor of claim 7 , wherein the driver further comprises:
a select transistor configured to output the signal of the drive transistor as the pixel signal based on a selection signal to select a pixel from among the plurality of pixels connected to a line, the select transistor having a source connected to a drain of the drive transistor.

9. The image sensor of claim 1 , wherein the logic circuits comprise:
a current source configured to convert a current into a voltage, the current being associated with the pixel signals, and the current source being a transistor that is substrate biased to the second voltage.

10. The image sensor of claim 1 , wherein the logic circuits further comprise:
an analog-to-digital converter block configured to,
perform correlated double sampling on the pixel signals,
compare each of the correlated sampled pixels input to a first terminal thereof

with a ramp signal input to a second terminal thereof, and generate a comparison signal based on a result thereof,
output the comparison signals, and
output a digital pixel signal by counting the comparison signals based on a clock signal.

11. An image processing device comprising:
a digital signal processor configured to process image data; and
an image sensor configured to output the image data, the image sensor including,
a plurality of pixels on a first region of a semiconductor substrate, the plurality of pixels configured to output pixel signals based on a received optical signal, the first region being substrate biased to a first voltage, and
logic circuits on a second region of the semiconductor substrate,

the second region being a different region from the first region, the logic circuits configured to output the pixel signals as the image data, the second region being substrate biased to a second voltage different from the first voltage, wherein the first voltage is a negative voltage.

12. The image processing device of claim 11 , wherein the second voltage is a ground voltage.

13. The image processing device of claim 11 , wherein each of the plurality of pixels comprises:
a photodiode configured to output a photocharge from the optical signal, the photodiode including a first impurity area having a first conductive type impurity and a second impurity area having a second conductive type impurity, the second impurity area surrounding the first impurity area, the second impurity area of the photodiode being in the first region of the semiconductor substrate, and the second impurity area having the first voltage applied thereto,
a sensing node adjacent to the photodiode, the sensing node configured to sense the photocharge, and
a driver configured to output the sensed photocharge as the pixel signals.

14. The image processing device of claim 11 , wherein the logic circuits comprise:
a current source configured to convert a current into a voltage, the current being associated with the pixel signals, and the current source being a transistor that is substrate biased to the second voltage.

15. An image sensor comprising:
a semiconductor substrate including,
a first region having one or more pixels connected to a first electrical path, the one or more pixels configured to accumulate photocharges to generate pixel signals based on a received incident light, and
a second region having logic circuits connected to a second electrical path, the second electrical path being a different path from the first electrical path, the logic circuits configured to output the pixel signals as image data, wherein the first electrical path supplies a negative voltage to the first region of the semiconductor substrate.

16. The image sensor of claim 15 , wherein the second electrical path supplies a ground voltage to the second region of the semiconductor substrate such that the first region is substrate biased to the negative voltage and the second region is substrate biased to a ground voltage.

17. The image sensor of claim 15 , wherein each pixel of the one or more pixels further comprises:
a photodiode configured to,
convert the received incident light to the photocharges, and
output the photocharges, and

transistors configured to sense the photocharges to output the pixel signal.

18. The image sensor of claim 17 , wherein the photodiode includes a first impurity area having a first conductive type impurity and a second impurity area having a second conductive type impurity, the second impurity area of the photodiode being in the first region of the semiconductor substrate and the second impurity area having the negative voltage applied thereto.

19. The image sensor of clam claim 18 , wherein the first impurity area is an n-type impurity area and the second impurity area is a p-type impurity area.

Assignees

• Kim Seung-Sik
• Lim Moo-Sup
• Lee Ji-Won
• Samsung Electronics Co Ltd

Inventors

• Kim Seung-Sik
• Lim Moo-Sup
• Lee Ji-Won

Classifications

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/583

  with different integration times · CPC title

• H04N25/621

  for the control of blooming · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H01L27/14654

  Electricity · mapped topic