Systems and methods to enable network communications for management controllers

Patent metadata

Field	Value
Publication number	US-9860189-B2
Application number	US-201514700891-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	Apr 30, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Systems and methods are provided that may be implemented to use memory as a shared interface between a management controller (e.g., such as embedded baseboard management controller “BMC”, embedded service processor, non-embedded management controller, etc.) and a network controller of an information handling system (e.g., such as a server) in order to achieve a relatively high speed data path between a network and the management controller, and without requiring the use and/or presence of a high speed physical connection to and/or from a sideband interface of the network controller.

First claim

What is claimed is:

1. An information handling system, comprising:
a processing device configured as a network interface controller (NIC), the NIC being configured to be coupled to intercept and exchange all incoming and outgoing network data packets transferred between any components of the information handling system and a network that is external to the information handling system, the NIC being configured to operate at the physical layer and data link layer to perform MAC address filtering for incoming packets to the information handling system:
main system memory;
a host processing device coupled between the NIC and the main system memory with the NIC coupled between the host processing device and the external network;
an additional processing device configured as a service processor or baseboard management controller (BMC) that is a separate processing device from the host processing device and the NIC, the additional processing device being coupled to the host processing device with the host processing device being coupled between the additional processing device and the NIC; and
additional memory for the additional processing device, the additional processing device memory coupled to the additional processing device with the additional processing device being coupled between the additional memory and the host processing device, and the additional processing device memory being separate from the main system memory;
where one or more of the processing devices of the system are configured to provide incoming network data packets filtered by the NIC as destined for the MAC address of the additional processing device from the network controller to the additional processing device through the additional processing device memory; and
where one or more of the processing devices of the system are configured to provide outgoing network data packets from the additional processing device to the NIC through the additional processing device memory, where the main system memory is DRAM and the additional processing device memory is DRAM; and
where one or more of the processing devices of the system are configured to:
receive incoming network packets from the external network in the NIC;
provide the received incoming network data packets filtered by the NIC for the additional processing device from the NIC to a receive buffer allocated for these filtered incoming network data packets in an area of the main system memory that is in a memory map of the host processing device by system BIOS executing on the host processing device, then transfer the incoming network data packets from the receive buffer of the main system memory to the additional processing device memory, and then transfer the incoming network data packets from the additional processing device memory to the additional processing device; and
provide outgoing network data packets from the additional processing device to the additional processing device memory, then transfer the outgoing network data packets from the additional processing device memory to a transmit buffer allocated for these outgoing network data packets in an area of the main system memory for the outgoing network data packets that is in the memory map of the host processing device by system BIOS executing on the host processing device, and then transfer the outgoing network data packets from the transmit buffer of the main system memory to the NIC for transmission to the external network.

2. The information handling system of claim 1 , where one or more of the processing devices of the system are configured to:
provide the incoming network data packets from the NIC to the host processing device, then transfer the incoming network data packets directly from the host processing device to the additional processing device memory, and then transfer the incoming network data packets from the additional processing device memory to the additional processing device; and
provide outgoing network data packets from the additional processing device to the memory controller memory, then transfer the outgoing network data packets directly from the memory controller memory to the host processing device, and then transfer the outgoing network data packets from the host processing device to the NIC for transmission to the external network.

3. The information handling system of claim 1 , where one or more of the processing devices of the system are configured to use direct memory access (DMA) to:
provide the incoming network data packets from the NIC to the receive buffer of the main system memory, transfer the incoming network data packets from the receive buffer of the main system memory to the additional processing device memory by direct memory access, and then transfer the incoming network data packets from the additional processing device memory to the additional processing device; and
provide the outgoing network data packets from the additional processing device to the memory controller memory, then transfer the outgoing network data packets from the memory controller memory to the transmit buffer of the main system memory, and then transfer the outgoing network data packets from the transmit buffer of the main system memory to the NIC for transmission to the external network.

4. The information handling system of claim 3 , further comprising a DMA controller that is part of a DMA channel that is coupled between the main system memory and the additional processing device memory, the DMA channel and its DMA controller being located completely outside the host processing device and completely outside the additional processing device; and where the one or more processing devices are configured to:
transfer the incoming network data packets from the receive buffer of the main system memory through the DMA channel and its DMA controller to the additional processing device memory by direct memory access before transferring the incoming network data packets from the additional processing device memory to the additional processing device memory; and
provide the outgoing network data packets from the additional processing device memory through the DMA channel and its DMA controller to the transmit buffer of the main system memory before transferring the outgoing network data packets from the transmit buffer of the main system memory to the NIC for transmission to the external network.

5. The information handling system of claim 1 , where the host processing device and the additional processing device are coupled together by a digital IO communication path; and where the host processing device is configured to send an interrupt request across the digital IO signal interface to notify the additional processing device when one or more of the received incoming packets are available to be read by the additional processing device from the additional processing device memory; and where the additional processing device is configured to send an interrupt request across the digital IO signal interface to notify the host processing device when one or more of the outgoing packets are available to be read and retrieved from the transmit buffer allocated in the system main memory.

6. The information handling system of claim 5 , further comprising a chipset, the host processing device and the additional processing device being integrated components of the chipset; where the additional processing device memory is on-chip internal memory of the additional processing device; and where the host processing device and the additional processing device are coupled together on the chipset by the digital IO communication path.

7. The information handling system of claim 1 , where the NIC is coupled to the additional processing device by a sideband interface connection; and
where the host proces

Assignees

• Butcher Wade A
• Holmberg Richard L
• Jreij Elie A
• Lambert Timothy M
• Dell Products Lp

Inventors

• Butcher Wade A
• Holmberg Richard L
• Jreij Elie A
• Lambert Timothy M

Classifications

• H04L41/04

  Network management architectures or arrangements · CPC title

• H04L47/78 Primary

  Architectures of resource allocation · CPC title

• H04L41/344

  Out-of-band transfers · CPC title