Semiconductor Device and Manufacturing Method Thereof
US-2015340513-A1 · Nov 26, 2015 · US
US9859441B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9859441-B2 |
| Application number | US-201615229363-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 5, 2016 |
| Priority date | Jul 31, 2008 |
| Publication date | Jan 2, 2018 |
| Grant date | Jan 2, 2018 |
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In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a gate electrode comprising copper over a substrate having an insulating surface; a first insulating film comprising silicon nitride over the gate electrode; a second insulating film over and in contact with the first insulating film, the second insulating film comprising silicon oxide; an oxide semiconductor layer over the second insulating film; a third insulating film over the oxide semiconductor layer; a conductive film comprising titanium over the oxide semiconductor layer, a fourth insulating layer over the conductive film, the fourth insulating layer comprising silicon oxide; a fifth insulating layer over the fourth insulating layer, the fifth insulating layer comprising silicon nitride; a sixth insulating layer over the fifth insulating layer, the sixth insulating layer comprising an organic material; and a pixel electrode electrically connected to the conductive film, wherein a thickness of the oxide semiconductor layer in a first region in which the oxide semiconductor layer and the conductive film are in contact with each other is smaller than a thickness of the oxide semiconductor layer in a second region in which the oxide semiconductor layer and the third insulating film are in contact with each other and overlap with at least part of the gate electrode, and wherein the conductive film is in contact with the first region of the oxide semiconductor layer and part of a top surface of the third insulating film. 2. The semiconductor device according to claim 1 , wherein part of the conductive film is formed over the third insulating film. 3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes at least In, Ga and Zn. 4. The semiconductor device according to claim 1 , wherein the first insulating film includes a halogen element, and the concentration of the halogen element is from 1×10 15 cm −3 to 1×10 20 cm −3 . 5. The semiconductor device according to claim 1 , wherein the second insulating film includes a halogen element, and the concentration of the halogen element is from 1×10 15 cm −3 to 1×10 20 cm −3 . 6. The semiconductor device according to claim 1 , wherein the conductive film is a stacked film including a titanium film and an aluminum film. 7. A semiconductor device comprising: a gate electrode comprising copper over a substrate; a first insulating layer over the gate electrode, the first insulating layer comprising silicon nitride; a second insulating layer over the first insulating layer, the second insulating layer comprising silicon oxide; an oxide semiconductor layer comprising indium, over the gate electrode with the first insulating layer and the second insulating layer interposed therebetween; a third insulating layer on and in contact with the oxide semiconductor layer, the third insulating layer comprising silicon oxide; a source electrode and a drain electrode over the oxide semiconductor layer and the third insulating layer, wherein each of the source electrode and the drain electrode comprises a conductive film comprising copper; a fourth insulating layer over the source electrode and the drain electrode, the fourth insulating layer comprising silicon oxide; a fifth insulating layer over the fourth insulating layer, the fifth insulating layer comprising silicon nitride; a sixth insulating layer over the fifth insulating layer, the sixth insulating layer comprising an organic material; and a pixel electrode electrically connected to the source electrode or the drain electrode, wherein a thickness of the oxide semiconductor layer in a first region in which the oxide semiconductor layer and the source or drain electrode are in contact with each other is smaller than a thickness of the oxide semiconductor layer in a second region in which the oxide semiconductor layer and the third insulating layer are in contact with each other. 8. The semiconductor device according to claim 7 , wherein the oxide semiconductor layer includes at least indium, gallium and zinc. 9. The semiconductor device according to claim 7 , wherein the second insulating layer is in contact with the fourth insulating layer. 10. The semiconductor device according to claim 7 , wherein the first insulating layer includes a halogen element, and the concentration of the halogen element is from 1×10 15 cm −3 to 1×10 20 cm −3 . 11. The semiconductor device according to claim 7 , wherein the substrate is a glass substrate. 12. The semiconductor device according to claim 7 , further comprising an FPC connected to the substrate.
being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title
Oxides · CPC title
using physical deposition, e.g. vacuum deposition or sputtering · CPC title
characterised by the gate electrodes · CPC title
Electricity · mapped topic
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