Semiconductor device having a chip under package

Patent metadata

Field	Value
Publication number	US-9859251-B2
Application number	US-201615012086-A
Country	US
Kind code	B2
Filing date	Feb 1, 2016
Priority date	Feb 2, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
an electronic component;
an electrical interconnect attached to the electronic component, the electrical interconnect having a first main face facing the electronic component and a second main face opposite the first main face;
external terminals disposed at the second main face of the electrical interconnect;
an encapsulant embedding a top surface and side surfaces of the electronic component such that a bottom surface of the electronic component is in a same plane as a bottom surface of the encapsulant and the bottom surface of the encapsulant contacts the first main face of the electrical interconnect; and
a first semiconductor chip facing the second main face of the electrical interconnect,
wherein the electrical interconnect is configured to electrically couple the electronic component to the external terminals,
wherein a height of the external terminals is at least as great as a thickness of the first semiconductor chip so that the first semiconductor chip can be mounted to a planar application board at a side of the first semiconductor chip opposite the electrical interconnect.

2. The semiconductor device package of claim 1 , wherein the first semiconductor chip is void of the encapsulant.

3. The semiconductor device package of claim 1 , wherein the first semiconductor chip is mounted to the electrical interconnect.

4. The semiconductor device package of claim 1 , wherein the electrical interconnect is an electrical redistribution structure.

5. The semiconductor device package of claim 1 , wherein the first semiconductor chip is a power semiconductor chip.

6. The semiconductor device package of claim 1 , wherein the first semiconductor chip is a vertical device having at least a first chip electrode at a first main face of the first semiconductor chip facing the electrical interconnect and having at least a second electrode at a second main face opposite the first main face.

7. The semiconductor device package of claim 1 , further comprising:
an underfill material arranged between the electrical interconnect and the first semiconductor chip.

8. The semiconductor device package of claim 1 , further comprising:
a second semiconductor chip facing the second main face of the electrical interconnect.

9. The semiconductor device package of claim 8 , wherein the first semiconductor chip and the second semiconductor chip are arranged in a laterally spaced relationship or in a stacked relationship.

10. The semiconductor device package of claim 1 , wherein the electrical interconnect is configured to electrically connect the first semiconductor chip to the external terminals of the semiconductor device package.

11. The semiconductor device package of claim 1 , wherein the electrical interconnect is configured to electrically connect the first semiconductor chip to the electronic component.

12. The semiconductor device package of claim 1 , wherein the electronic component is a semiconductor chip which comprises one of a logic circuit, a driver circuit, a power circuit and an integrated passive device.

13. The semiconductor device package of one claim 1 , wherein the semiconductor device comprises a voltage converter.

14. A semiconductor device assembly, comprising:
a semiconductor device package comprising:
an electronic component;
an electrical interconnect attached to the electronic component, the electrical interconnect having a first main face facing the electronic component and a second main face opposite the first main face;
external terminals disposed at the second main face of the electrical interconnect;
an encapsulant embedding a top surface and side surfaces of the electronic component such that a bottom surface of the electronic component is in a same plane as a bottom surface of the encapsulant and the bottom surface of the encapsulant contacts the first main face of the electrical interconnect; and
a first semiconductor chip facing the second main face of the electrical interconnect, the electrical interconnect configured to electrically couple the electronic component to the external terminals;

a planar application board on which the semiconductor device package is mounted; and
a thermally conducting material disposed between the first semiconductor chip and the application board,
wherein a height of the external terminals is at least as great as a thickness of the first semiconductor chip so that the first semiconductor chip is mounted to the planar application board at a side of the first semiconductor chip opposite the electrical interconnect.

15. The semiconductor device assembly of claim 14 , wherein the thermally conducting material is electrically conducting.

16. The semiconductor device assembly of claim 15 , wherein the thermally conducting material is a solder material or an electrically conducting adhesive.

17. The semiconductor device assembly of claim 14 , wherein the thermally conducting material is electrically insulating.

18. The semiconductor device assembly of claim 17 , wherein the thermally conducting material is a polymer material filled with ceramic particles.

19. The semiconductor device assembly of claim 14 , wherein the application board comprises electrically conducting vias in an area beneath the first semiconductor chip.

20. A method of assembling a semiconductor device package to a planar application board, the method comprising:
providing a semiconductor device package comprising an electronic component, an electrical interconnect attached to the electronic component, the electrical interconnect having a first main face facing the electronic component and a second main face opposite the first main face, external terminals disposed at the second main face of the electrical interconnect, and a first semiconductor chip facing the second main face of the electrical interconnect, the electrical interconnect configured to electrically couple the electronic component to the external terminals,
wherein an encapsulant is applied to a top surface and side surfaces of the electronic component prior to attaching the electrical interconnect to the electronic component such that bottom electrodes of the electronic component facing the first main face of the electrical interconnect remain exposed after application of the encapsulant;
depositing a thermally conducting material on an area of the planar application board;
placing the semiconductor device package over the area on the application board; and
electrically and mechanically connecting the semiconductor device package to the application board, wherein the thermally conducting material interconnects the first semiconductor chip to the area of the application board, wherein a height of the external terminals is at least as great as a thickness of the first semiconductor chip so that the first semiconductor chip is mounted to the planar application board at a side of the first semiconductor chip opposite the electrical interconnect.

21. The method of claim 20 , wherein:
the thermally conducting material is a solder material; and
electrically and mechanically connecting the semiconductor device package to the application board comprises soldering the first semiconductor chip to the area of the application board via the solder material.

22. The semiconductor device package of claim 1 , wherein chip pads located on the bottom surface of the electronic component attach to corresponding through-connections l

Assignees

• Infineon Technologies Ag

Inventors

• Beer Gottfried
• Ossimitz Peter

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9413

  on encapsulations · CPC title