Method of fabricating an electronic package

Patent metadata

Field	Value
Publication number	US-9859249-B2
Application number	US-201414778111-A
Country	US
Kind code	B2
Filing date	Dec 3, 2014
Priority date	Dec 3, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Some example forms relate a method of fabricating an electronic package. The method includes attaching a source wafer that includes micro devices to a target wafer. The method further includes removing a portion of the source wafer from the target wafer to form an electronic package. The micro devices remain on the target wafer when the source wafer is removed from target wafer. The method may further include performing post processing on the electronic package that is formed after the source wafer is removed from the target wafer. In some forms of the method, some of the micro devices remain on the source wafer when the source wafer is removed from target wafer.

First claim

The invention claimed is:

1. A method comprising:
attaching a source wafer that includes micro devices to a target wafer; and
removing a portion of the source wafer from the target wafer to form an electronic package, wherein the micro devices remain on the target wafer when the source wafer is removed from target wafer, wherein attaching a source wafer that includes micro devices to a target wafer includes attaching the micro devices to respective dielectric pedestals that extend from a surface of the target wafer, wherein attaching a source wafer that includes micro devices to a target wafer includes attaching the micro devices to solder bumps that extend from a surface of the target wafer and engaging the micro devices with stops that extend from a surface of the target wafer.

2. A method comprising:
attaching a source wafer that includes micro devices to a target wafer; and
removing a portion of the source wafer from the target wafer to form an electronic package, wherein the micro devices remain on the target wafer when the source wafer is removed from target wafer, wherein attaching a source wafer that includes micro devices to a target wafer includes engaging the micro devices with stops that extend from a surface of the target wafer.

3. The method of claim 2 , wherein engaging the micro devices with stops that extend from a surface of the target wafer includes adhering the micro devices to the stops.

4. A method comprising:
attaching a source wafer that includes micro devices to a target wafer; and
removing a portion of the source wafer from the target wafer to form an electronic package, wherein the micro devices remain on the target wafer when the source wafer is removed from target wafer, wherein attaching a source wafer that includes micro devices to a target wafer includes attaching the micro devices to respective dies that are on a surface of the target wafer.

5. The method of claim 4 , wherein attaching a source wafer that includes micro devices to a target wafer includes attaching conductive pads on the micro devices with the target wafer.

6. The method of claim 4 , wherein attaching a source wafer that includes micro devices to a target wafer includes attaching the source wafer to conductive pads on the target wafer.

7. The method of claim 4 , wherein attaching a source wafer that includes micro devices to a target wafer includes attaching conductive pads on the micro devices with conductive pads on the source wafer.

8. The method of claim 1 , wherein attaching a source wafer that includes micro devices to a target wafer includes attaching conductive pads on the micro devices with solder bumps that are mounted on conductive pads on the target wafer.

9. The method of claim 1 , further comprising performing post processing on the electronic package that is formed after the source wafer is removed from the target wafer.

10. The method of claim 1 , wherein some of the micro devices remain on the source wafer when the source wafer is removed from target wafer.

11. The method of claim 10 , wherein the target wafer includes connecting sections that are part of the target wafer, wherein attaching the source wafer that includes micro devices to the target wafer includes attaching each of connecting sections to the target wafer.

12. A method comprising:
attaching a source wafer that includes micro devices to a target wafer, wherein the micro devices include conductive pads and the target wafer includes a dielectric pedestal on a surface of the target wafer; and
removing a portion of the source wafer from the target wafer to form an electronic package, wherein the conductive pads on micro devices engage the die on the target wafer when the source wafer is removed from target wafer.

13. The method of claim 12 , wherein the target wafer includes dielectric pedestals such that the conductive pads on some of micro devices engage the dielectric pedestals on the target wafer when the source wafer is removed from target wafer.

14. The method of claim 12 , wherein some of the micro devices remain on the source wafer when the source wafer is removed from target wafer.

15. A method comprising:
attaching a source wafer that includes micro devices to conductive pads on surface of a target wafer, wherein attaching the source wafer includes engaging the micro devices with stops that extend from a surface of the target wafer and attaching the micro devices to solder bumps that extend from the conductive pads on the target wafer; and
removing a portion of the source wafer from the source wafer to form an electronic package, wherein the micro devices are attached to the solder bumps when the source wafer is removed from target wafer.

16. The method of claim 15 , wherein attaching the source wafer includes attaching conductive pads on the micro device with the solder bumps on the target wafer.

17. The method of claim 15 , wherein some of the micro devices remain on the source wafer when the source wafer is removed from target wafer.

Assignees

• Intel Corp

Inventors

• Chang Peter
• Mayberry Michael

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/0198 Primary

  batch processes · CPC title

• H10W72/07337

  using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07207

  Temporary substrates, e.g. removable substrates · CPC title