Semiconductor package device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9859232-B1
Application number	US-201615344392-A
Country	US
Kind code	B1
Filing date	Nov 4, 2016
Priority date	Nov 4, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

The present disclosure provides a semiconductor package device comprising a substrate, a semiconductor device, a first electronic component, an antenna pattern and a first package body. The substrate has a first area and a second area. The semiconductor device is disposed on the first area of the substrate. The first electronic component is disposed on the second area of the substrate. The antenna pattern is disposed on the second area of the substrate and electrically connected to the first electronic component. The first package body encapsulates the first area of the substrate and the semiconductor device and exposes the antenna pattern, the first electronic component and the second area of the substrate.

First claim

What is claimed is:

1. A semiconductor package device, comprising:
a substrate having a first area and a second area;
a semiconductor device on the first area of the substrate;
an antenna pattern on the second area of the substrate;
a first electronic component on the antenna pattern and electrically connected to the antenna pattern; and
a first package body encapsulating the first area of the substrate and the semiconductor device and exposing the antenna pattern, the first electronic component and the second area of the substrate.

2. The semiconductor package device according to claim 1 , further comprising a second package body encapsulating the second area of the substrate and the antenna pattern.

3. The semiconductor package device according to claim 1 , further comprising a second electronic component on the second area of the substrate and a third electronic component on the second area of the substrate, wherein the antenna pattern further comprises:
a feeding line electrically connected to the semiconductor device;
a first line segment electrically connected to the feeding line by the first electronic component;
a second line segment electrically connected to the feeding line by the second electronic component; and
a third line segment electrically connected to the second line segment by the third electronic component.

4. The semiconductor package device according to claim 1 , wherein a ratio of a width of the second area of the substrate to an operating wavelength of the antenna pattern is less than about 0.013.

5. The semiconductor package device according to claim 1 , wherein a ratio of a width of the second area of the substrate to a length of the second area of the substrate is less than about 0.25.

6. The semiconductor package device according to claim 1 , further comprising a shield on the first package body.

7. An electronic module, comprising:
a circuit board;
a first antenna pattern on the circuit board; and
a semiconductor package device on the circuit board, comprising:
a substrate comprising a first area and a second area;
a semiconductor device on the first area of the substrate; and
a second antenna pattern on the second area of the substrate and electrically connected to the first antenna pattern on the circuit board.

8. The electronic module according to claim 7 , further comprising a first electronic component on the circuit board, wherein the first antenna pattern further comprises a first line segment and a second line segment electrically connected to the first line segment by the first electronic component.

9. The electronic module according to claim 8 , wherein the first electronic component is a variable capacitor.

10. The electronic module according to claim 8 , further comprising a second electronic component on the substrate and a third electronic component on the substrate, wherein the second antenna pattern further comprises a third line segment electrically connected to the first line segment of the first antenna pattern, a feeding line electrically connected to the third line segment by the second electronic component on the substrate, and a fourth line segment electrically connected to the feeding line by the third electronic component on the substrate.

11. The electronic module according to claim 10 , further comprising a conductive pattern formed on a sidewall surface of the second area of the substrate, wherein the third line segment of the second antenna pattern is electrically connected to the first line segment of the first antenna pattern by the conductive pattern.

12. The electronic module according to claim 10 , wherein the substrate comprises a conductive via, and the third line segment of the second antenna pattern is electrically connected to the first line segment of the first antenna pattern by the conductive via in the substrate, wherein the conductive via is beneath the third electronic component.

13. The electronic module according to claim 7 , wherein a ratio of a width of the second area of the substrate to an operating wavelength of the first and second antenna patterns is less than about 0.013.

14. The electronic module according to claim 7 , wherein a ratio of a width of the second area of the substrate to a length of the second area of the substrate is less than about 0.25.

15. The electronic module according to claim 7 , wherein the semiconductor package device is disposed at a middle and along an edge of the circuit board.

16. The electronic module according to claim 7 , wherein the semiconductor package device is disposed at a corner of the circuit board.

17. A semiconductor package device, comprising:
an antenna pattern comprising a feeding line, a first line segment, a second line segment and a third line segment, wherein the feeding line is disposed between the first line segment and the second line segment, and the second line segment is disposed between the feeding line and the third line segment;
a first electronic component electrically connecting the first line segment and the feeding line;
a second electronic component electrically connecting the feeding line and the second line segment; and
a third electronic component electrically connecting the second line segment and the third line segment.

18. The semiconductor package device according to claim 17 , further comprising:
a substrate comprising a first area, a second area, a first via and a second via, wherein the antenna pattern, the first electronic component, the second electronic component and the third electronic component are disposed on the second area of the substrate, the first via is formed beneath the first electronic component, and the second via is formed beneath the third electronic component; and
a semiconductor device disposed on the first area of the substrate.

19. The semiconductor package device according to claim 18 , further comprising:
a package body covering the first area of the substrate and exposing the second area of the substrate; and
a shield on the package body.

20. The semiconductor package device according to claim 17 , further comprising a fourth electronic component, wherein the antenna pattern further comprises a fourth line segment electrically connected to the feeding line via the fourth electronic component, wherein the fourth line segment is substantially parallel to the second line segment.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chiang Chung-Hsin
• Chi Kuang-Ting
• Cheng Ming-Hsiang

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/209

  Vertical interconnections, e.g. vias · CPC title