Laminated chip having microelectronic element embedded therein

Patent metadata

Field	Value
Publication number	US-9859220-B2
Application number	US-201615131966-A
Country	US
Kind code	B2
Filing date	Apr 18, 2016
Priority date	Jul 23, 2010
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

First claim

The invention claimed is:

1. A method of making a microelectronic structure, the method comprising:
providing a substrate having a first region with circuitry comprising semiconductor circuit elements and comprising first contacts, the first region having a body region with a top surface and a bottom surface, the first contacts being at the top surface, the first region comprising a cavity extending into the body region from the bottom surface, the cavity having a bottom-facing cavity floor surface, the first region having floor surface pads adjacent the cavity floor surface, the first region having first via conductors extending into the body region from the cavity floor surface, each first via conductor being electrically connected to at least one floor surface pad;
attaching a semiconductor chip to the first region so that the semiconductor chip is at least partially disposed within the cavity, the semiconductor chip having a top surface facing toward the cavity floor surface of the first region, and a bottom surface facing in the same direction as the bottom surface of the first region, the semiconductor chip having top contacts at the top surface, wherein the attaching comprises bonding each top contact to at least one floor surface pad;
providing a dielectric encapsulant at least within the cavity and around the semiconductor chip, the dielectric encapsulant physically bonding the semiconductor chip to the first region;
after the attaching and the providing dielectric encapsulant, forming a continuous planar bottom surface including bottom surfaces of the substrate and at least one of the dielectric encapsulant and the semiconductor chip, wherein forming the continuous planar bottom surface comprises simultaneous removal of material from at least two of (i) the substrate, (ii) the semiconductor chip, and (iii) the dielectric encapsulant.

2. The method of claim 1 wherein the simultaneous removal of material comprises simultaneous removal of material from the substrate and the semiconductor chip.

3. The method of claim 1 wherein the simultaneous removal of material comprises simultaneous removal of material from the substrate and the dielectric encapsulant.

4. The method of claim 1 wherein the simultaneous removal of material comprises simultaneous removal of material from the semiconductor chip and the dielectric encapsulant.

5. The method of claim 1 wherein the simultaneous removal of material comprises simultaneous removal of material from the substrate, the semiconductor chip, and the dielectric encapsulant.

6. The method of claim 1 further comprising forming second via conductors and bottom pads, each bottom pad being located at the planar bottom surface, each second via conductor being electrically connected to a bottom pad and extending from the planar bottom surface into at least one of (i) the substrate, (ii) the semiconductor chip, and (iii) the dielectric encapsulant.

7. The method of claim 6 wherein at least one second via conductor extends into the body region and lies outside the cavity.

8. The method of claim 6 wherein at least one second via conductor extends into the semiconductor chip.

9. The method of claim 6 wherein at least one second via conductor extends into the dielectric encapsulant and is spaced from the semiconductor chip.

10. The method of claim 6 wherein the bottom pads are formed after forming the planar bottom surface; and
each second via conductor comprises a portion beginning at the planar bottom surface and extending upward from the planar bottom surface, the portion being formed after forming the planar bottom surface.

11. The method of claim 10 wherein each said portion is formed in a via beginning at the planar bottom surface and extending upward from the planar bottom surface, the via being formed after forming the planar bottom surface.

12. The method of claim 1 wherein the first region has active circuit elements integral with the body and disposed in an active layer adjacent the top surface, and at least one first via conductor reaches the active layer.

13. The method of claim 12 wherein at least one first via conductor extends into the active layer between the active circuit elements.

Assignees

• Tessera Inc

Inventors

• Oganesian Vage
• Mohammed Ilyas
• Mitchell Craig
• Haba Belgacem
• Savalia Piyush

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title