Chip capacitor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9859061-B2
Application number	US-201214372741-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Jan 17, 2012
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

[Theme] To provide a chip capacitor capable of easily and rapidly accommodating a plurality of types of capacitance values using a common design and a method for manufacturing the chip capacitor. [Solution] A chip capacitor 1 includes a substrate 2 , a first external electrode 3 , a second external electrode 4 , capacitor elements C 1 to C 19 , and fuses F 1 to F 9 disposed on the substrate 2 . The capacitor elements C 1 to C 19 respectively include a first electrode film 11 , a first capacitance film 12 on the first electrode film 11 , a second electrode film 13 disposed on the first capacitance film 12 and facing the first electrode film 11 , a second capacitance film 17 on the second electrode film 13 , and a third electrode film 16 disposed on the second capacitance film 17 and facing the second electrode film 13 and are connected between the first external electrode 3 and the second external electrode 4 . The fuses F 1 to F 9 are each interposed between the capacitor elements C 1 to C 19 and the first external electrode 3 or the second external electrode 4 and are capable of disconnecting each of the capacitor elements C 1 to C 19.

First claim

What is claimed is:

1. A chip capacitor comprising:
a substrate having a front surface and a rear surface, the substrate made of a silicon;
a first external electrode disposed only on the front surface of the substrate;
a second external electrode disposed only on the front surface of the substrate;
a plurality of capacitor elements, respectively including a first electrode film formed on the substrate, a first capacitance film formed on the first electrode film, a second electrode film formed on the first capacitance film so as to face the first electrode film, a second capacitance film formed on the second electrode film, and a third electrode film formed on the second capacitance film so as to face the second electrode film, and being connected between the first external electrode and the second external electrode;
a plurality of fuses that are formed on the substrate, are each interposed between the plurality of capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the plurality of capacitor elements; and
an insulating film covering the front surface and a side surface of the substrate, the insulating film having a first opening and a second opening, wherein
the first external electrode and the second external electrode project upwardly from the first opening and the second opening, respectively,
the insulating film is exposed on the side surface of the substrate and has an exposed portion which is not covered with the first external electrode and the second external electrode on the side surface of the substrate, and
the rear surface of the substrate is a polishing surface.

2. The chip capacitor according to claim 1 , wherein the plurality of capacitor elements have mutually different capacitance values.

3. The chip capacitor according to claim 2 , wherein the capacitance values of the plurality of capacitor elements are set to form a geometric progression.

4. The chip capacitor according to claim 1 , wherein at least one of the plurality of fuses is cut.

5. The chip capacitor according to claim 1 , wherein the second electrode film is divided into a plurality of second electrode film portions and the plurality of fuses are connected respectively to the plurality of the second electrode film portions.

6. The chip capacitor according to claim 5 , wherein the plurality of second electrode film portions face the first electrode film and the third electrode film over mutually different facing areas.

7. The chip capacitor according to claim 6 , wherein the facing areas of the plurality of second electrode film portions are set to form a geometric progression.

8. The chip capacitor according to claim 5 , wherein the fuses and the first electrode film, the second electrode film, or the third electrode film are formed of films of the same conductive material.

9. The chip capacitor according to claim 1 , wherein the first electrode film is divided into a plurality of first electrode film portions and the plurality of fuses are connected respectively to the plurality of the first electrode film portions.

10. The chip capacitor according to claim 9 , wherein the plurality of first electrode film portions face the second electrode film over mutually different facing areas.

11. The chip capacitor according to claim 10 , wherein the facing areas of the plurality of first electrode film portions are set to form a geometric progression.

12. The chip capacitor according to claim 1 , wherein the third electrode film is divided into a plurality of third electrode film portions and the plurality of fuses are connected respectively to the plurality of the third electrode film portions.

13. The chip capacitor according to claim 12 , wherein the plurality of third electrode film portions face the second electrode film over mutually different facing areas.

14. The chip capacitor according to claim 13 , wherein the facing areas of the plurality of third electrode film portions are set to form a geometric progression.

15. The chip capacitor according to claim 1 , wherein the plurality of fuses are disposed with the positions thereof being shifted so as not to overlap with each other in a plan view of looking down at a principal surface of the substrate perpendicularly.

16. A method for manufacturing a chip capacitor comprising:
a step of forming a plurality of capacitor elements on a substrate having a front surface and a rear surface, the substrate made of a silicon;
a step of forming a first external electrode disposed only on the front surface of the substrate and a second external electrode disposed only on the front surface of the substrate on the substrate; and
a step of forming, on the substrate, a plurality of fuses that disconnectably connect each of the plurality of capacitor elements to the first external electrode or the second external electrode; and
wherein the step of forming the plurality of capacitor elements includes:
a step of forming a first electrode film on the substrate;
a step of forming a first capacitance film on the first electrode film;
a step of forming a second electrode film on the first capacitance film so as to face the first electrode film;
a step of forming a second capacitance film on the second electrode film;
a step of forming a third electrode film on the second capacitance film so as to face the second electrode film;
a step of dividing at least one among the first electrode film, the second electrode film, and the third electrode film into a plurality of electrode film portions; and
a step of forming an insulating film covering the front surface and a side surface of the substrate, the insulating film having a first opening and a second opening,
wherein the first external electrode and the second external electrode project upwardly from the first opening and the second opening, respectively,
the insulating film is exposed on the side surface of the substrate and has an exposed portion which is not covered with the first external electrode and the second external electrode on the side surface of the substrate, and
the rear surface of the substrate is a polishing surface.

17. The method for manufacturing a chip capacitor according to claim 16 , wherein the fuses are formed so as to be connected respectively to the plurality of electrode film portions.

18. The method for manufacturing a chip capacitor according to claim 16 , wherein the plurality of electrode film portions are formed so as to face the electrode film, being faced across the first capacitance film or the second capacitance film, over mutually different facing areas.

19. The method for manufacturing a chip capacitor according to claim 18 , wherein the facing areas of the plurality of electrode film portions are set to form a geometric progression.

20. The method for manufacturing a chip capacitor according to claim 16 , wherein the plurality of fuses are formed with the positions thereof being shifted so as not to overlap with each other in a plan view of looking down at a principal surface of the substrate perpendicularly.

21. The method for manufacturing a chip capacitor according to claim 16 , wherein the fuses and the first electrode film, the second electrode film, or the third electrode film are formed of films of the same conductive material.

22. The method for manufacturing a chip capacitor according to claim 16 , further comprising a fuse cutting step of cutting at least one of the plurality of

Assignees

• Rohm Co Ltd

Inventors

• Okada Hiroyuki
• Fuwa Yasuhiro

Classifications

• H01G4/015

  Special provisions for self-healing · CPC title

• H01G5/011 Primary

  Electrodes · CPC title

• H01G5/38

  Multiple capacitors, e.g. ganged · CPC title

• H01G4/40

  Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

• H01G4/385 Primary

  Single unit multiple capacitors, e.g. dual capacitor in one coil · CPC title