Hardware-based performance equalization for storage devices

Patent metadata

Field	Value
Publication number	US-9858990-B2
Application number	US-201414574527-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.

First claim

The invention claimed is:

1. An apparatus, comprising:
a register memory configured to hold multiple minimal values specified for a performance measure of respective different types of memory access commands, wherein actual performance measures of the memory access commands vary among memory devices; and
circuitry configured to: receive a memory access command; identify a type of the received memory access command; execute the received memory access command in one or more memory devices; and acknowledge the memory access command, wherein the acknowledgement is sent after a time period corresponding to the respective minimal value stored in the register memory for the identified type of access command, has passed from receiving the memory access command.

2. The apparatus according to claim 1 , wherein the memory access commands comprise write commands, and wherein the performance measure comprises write duration.

3. The apparatus according to claim 1 , wherein the performance measure comprises a duration of executing the memory access commands, and wherein the circuitry is configured to: initialize a timer to measure the respective minimal value stored in the register memory; start the timer upon receiving the memory access command for execution, and acknowledge the memory access command not before the timer expires.

4. The apparatus according to claim 1 , wherein the register memory or the circuitry is configured to reconfigure the minimal value in response to an external instruction.

5. The apparatus according to claim 1 , wherein the register memory and the circuitry are integrated in the given memory device.

6. The apparatus according to claim 1 , wherein the register memory and the circuitry are integrated in a controller that stores data in the given memory device.

7. The apparatus according to claim 1 , wherein the register memory is configured to hold multiple minimal values specified for respective different types of memory access write commands, and wherein the circuitry is configured to: identify a type of a received memory access write command; and acknowledge the received memory access write command after a time period corresponding to the respective minimal value specified for the identified type has passed from receiving the memory access write command.

8. The apparatus according to claim 7 , wherein the register memory is configured to hold multiple minimal values specified for respective different types of memory access write commands including accesses to Least Significant Bit (LSB), Most significant Bit (MSB) and Upper Significant Bit (USB) pages.

9. The apparatus according to claim 7 , wherein the register memory is configured to hold multiple minimal values specified for respective different types of memory access write commands including single-plane write commands, multi-plane write commands, and cache-mode write commands.

10. A system, comprising:
one or more memory devices;
a processor; and
a performance equalization unit configured to:
hold multiple minimal values specified for a performance measure of respective different types of memory access commands, wherein actual performance measures of the memory access commands vary among memory devices;
receive from the processor a memory access command;
identify a type of the received memory access command;
execute the received memory access command in the one or more memory devices; and
acknowledge the memory access command, wherein the acknowledgement is sent after a time period corresponding to the respective minimal value stored in the register memory for the identified type of access command, has passed from receiving the memory access command.

11. The system according to claim 10 , wherein the memory access commands comprise write commands, and wherein the performance measure comprises write duration.

12. The system according to claim 10 , wherein the performance measure comprises a duration of executing the memory access commands, and wherein the performance equalization unit is configured to: initialize a timer to measure the respective minimal value stored in the register memory; start the timer upon receiving the memory access command for execution; and acknowledge the memory access command not before the timer expires.

13. The system according to claim 10 , wherein the performance equalization unit is configured to reconfigure the minimal value in response to an external instruction.

14. The system according to claim 10 , wherein the performance equalization unit is integrated in the one or more memory devices.

15. The system according to claim 10 , wherein the performance equalization unit is integrated in a memory controller that comprises the processor.

16. The system according to claim 10 , wherein the performance equalization unit is configured to: hold multiple minimal values specified for respective different types of the memory access write commands; identify a type of the received memory write access command; and acknowledge the received memory access write command after a time period corresponding to the respective minimal value specified for the identified type has passed from receiving the memory access write command.

17. A method, comprising:
holding in a register memory multiple minimal values specified for a performance measure of respective different types of memory access commands, whose actual performance measures vary among memory devices;
receiving a memory access command;
identifying a type of the received memory access command;
executing the received memory access command in one or more memory devices; and
acknowledging the memory access command, wherein the acknowledgement is sent after a time period corresponding to the respective minimal value for the identified type of access command, has passed from receiving the memory access command.

18. The method according to claim 17 , wherein the performance measure comprises a duration of executing the memory access commands, and wherein acknowledging the memory access command comprises initializing a timer to measure the respective minimal value stored in the register memory, starting the timer upon receiving the memory access command for execution, and acknowledging the memory access command not before the timer expires.

19. The method according to claim 17 , and comprising reconfiguring the minimal value in response to an external instruction.

20. The method according to claim 17 , wherein the different types of memory access commands comprise different types of write commands, and wherein the performance measure comprises write duration.

Assignees

• Apple Inc

Inventors

• Erez Liran
• Ben-Yehuda Guy
• Meir Avraham (Poza)
• Isachar Ori

Classifications

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title