Display driving apparatus and display driving method thereof

US9858898B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9858898-B2
Application numberUS-201615175047-A
CountryUS
Kind codeB2
Filing dateJun 7, 2016
Priority dateJan 24, 2013
Publication dateJan 2, 2018
Grant dateJan 2, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display driving apparatus including a signal transmission interface, a timing control circuit and an image detection circuit is provided. The signal transmission interface is configured to receive video image data and output the video image data. The timing control circuit is configured to receive the video image data and drive a display panel based on the video image data. The image detection circuit determines whether the video image data is a static image and determines whether the display driving apparatus operates in a power-saving mode based on the determination result. Under the power-saving mode, the signal transmission interface masks a part of the video image data, so as not to output the masked video image data to the timing control circuit. Furthermore, a display driving method adapted for the foregoing display driving apparatus is also provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A display driving apparatus, adapted to drive a display panel according to video image data, the display driving apparatus comprising: a signal transmission interface, receiving the video image data at a first rate and outputting the video image data; a timing control circuit, coupled to the signal transmission interface, receiving the video image data, and driving the display panel based on the video image data; and an image detection circuit, coupled to the signal transmission interface, receiving the video image data, determining whether the video image data is a static image, and determining whether the display driving apparatus enters a power saving mode based on a determination result, wherein in the power saving mode, the signal transmission interface continuously receives the video image data at the first rate, and periodically masks a part of the video image data according to the determination result and outputs an unmasked part of the video image data to the timing control circuit, wherein the display driving apparatus is a RAM-less display driving apparatus without frame buffers. 2. The display driving apparatus as claimed in claim 1 , wherein the video image data comprises a plurality of batches of frame data, and the signal transmission interface periodically masks a part of the frame data and outputs an unmasked part of the frame data in the video image data in the power saving mode. 3. The display driving apparatus as claimed in claim 2 , wherein the signal transmission interface further outputs a vertical synchronous signal to the timing control circuit, and in the power saving mode, the masked frame data is arranged at intervals in the frame data in a fixed timing length in response to the vertical synchronous signal. 4. The display driving apparatus as claimed in claim 2 , further comprising a gate driving circuit for providing a scan signal to drive the display panel, wherein in the power saving mode, the timing control circuit outputs a control signal in response to the masked frame data to disable the gate driving circuit. 5. A display driving method, adapted to a display driving apparatus for driving a display panel according to video image data, and the display driving method comprising: receiving the video image data at a first rate; determining whether the video image data is a static image; determining whether the display driving apparatus enters a power saving mode based on a determination result; continuously receiving the video image data at the first rate; periodically masking a part of the video image data according to the determination result in the power saving mode and outputting an unmasked part of the video image data; and driving the display panel according to the unmasked part of the video image data, wherein the display driving apparatus is a RAM-less display driving apparatus without frame buffers. 6. The display driving method as claimed in claim 5 , wherein the video image data comprises a plurality of batches of frame data, and the step of periodically masking the part of the video image data and outputting the unmasked part of the video image data comprises periodically masking a part of the frame data and outputting an unmasked part of the frame data in the video image data. 7. The display driving method as claimed in claim 6 , wherein the display panel is driven according to a vertical synchronous signal, and in the power saving mode, the masked frame data is arranged at intervals in the frame data in a fixed timing length in response to the vertical synchronous signal. 8. The display driving method as claimed in claim 6 , further comprising: providing a scan signal by a gate driving circuit, so as to drive the display panel; and outputting a control signal in response to the masked frame data to disable the gate driving circuit in the power saving mode.

Assignees

Inventors

Classifications

  • Detection of image changes, e.g. determination of an index representative of the image change · CPC title

  • Waveforms comprising zero voltage phase or pause · CPC title

  • Power saving in display device · CPC title

  • of display devices · CPC title

  • Power management, e.g. power saving · CPC title

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What does patent US9858898B2 cover?
A display driving apparatus including a signal transmission interface, a timing control circuit and an image detection circuit is provided. The signal transmission interface is configured to receive video image data and output the video image data. The timing control circuit is configured to receive the video image data and drive a display panel based on the video image data. The image detectio…
Who is the assignee on this patent?
Novatek Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification G09G5/18. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 02 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).