Source driver and display apparatus including the same

Patent metadata

Field	Value
Publication number	US-9858884-B2
Application number	US-201514734417-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Oct 10, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Disclosed is a display driver including an input pad configured to receive a supply voltage, a wiring line connected to the input pad, a digital-to-analog converter configured to output analog signals based on digital-to-analog conversion results of data, a plurality of output buffer units configured to buffer the analog signals, and a plurality of bias controllers connected to different positions of the wiring line. Each of the bias controllers independently controls a bias voltage of a corresponding one of the output buffer units based on the supply voltage supplied through the wiring line.

First claim

What is claimed is:

1. A display driver comprising:
an input pad configured to receive a supply voltage;
a wiring line connected to the input pad and configured to supply the supply voltage, the wiring line having a plurality of different positions or locations;
a digital-to-analog converter configured to convert digital signals to analog signals;
a plurality of output buffer units configured to receive a bias voltage and buffer the analog signals; and
a plurality of bias controllers connected to the positions or locations of the wiring line, wherein each of the bias controllers independently controls the bias voltage of one or more of the output buffer units from the supply voltage supplied by the wiring line, wherein a first one of the output buffer units and the wiring line are connected at a first node, a first bias controller corresponding to the first output buffer unit and the first wiring line are connected at a second node, and the first and second nodes are adjacent to each other.

2. The display driver according to claim 1 , wherein a wiring distance of each of the bias controllers from the input pad is shorter than a wiring distance of a corresponding one of the output buffer units from the input pad.

3. The display driver according to claim 1 , wherein a wiring distance of each of the bias controllers from the input pad is longer than a wiring distance of a corresponding one of the output buffer units from the input pad.

4. The display driver according to claim 1 , wherein each of the output buffer units includes a plurality of output buffers connected to the wiring line.

5. The display driver according to claim 4 , wherein each of the plurality of output buffers receives the bias voltage, and each of the bias controllers controls the bias voltage to each of the output buffers in a corresponding one of the output buffer units.

6. The display driver according to claim 4 , wherein each of the output buffer units further includes a plurality of bias transistors, and each of the bias transistors includes (i) a source and a drain connected between a corresponding one of the output buffers and the wiring line and (ii) a gate configured to be controlled by a corresponding one of the bias controllers.

7. The display driver according to claim 6 , wherein each of the bias controllers includes a first transistor including a first source connected to the wiring line, a first gate connected to the gates of the bias transistors in a corresponding one of the output buffer units, and a first drain connected to the first gate.

8. The display driver according to claim 7 , wherein each of the bias controllers further includes a reference current supply unit connected to the drain of the first transistor.

9. The display driver according to claim 8 , wherein each of the bias transistors and the first transistor form a current mirror.

10. The display driver according to claim 4 , wherein each of the bias controllers provides the supply voltage as the bias voltage through nodes where the output buffers in a corresponding one of the output buffer units and the wiring line are connected.

11. The display driver according to claim 4 , wherein each of the bias controllers and the wiring line are connected at a first node, the output buffers in a corresponding one of the output buffer units and the wiring line are connected at second nodes, and each of the first nodes is located between subsets of each of the corresponding second nodes.

12. The display driver according to claim 11 , wherein the second nodes are symmetrical with respect to the first node.

13. The display driver according to claim 1 , further comprising:
a latch unit configured to store data; and
a level shifter configured to convert a voltage level of the data from the latch unit and to provide the digital-to-analog converter with the data having the converted voltage level.

14. A display driver comprising:
a first input pad configured to receive a first supply voltage;
a second input pad configured to receive a second supply voltage;
a first wiring line connected to the first input pad;
a second wiring line connected to the second input pad;
a digital-to-analog converter configured to convert digital signals to analog signals;
a plurality of output buffer units configured to buffer the analog signals; and
a plurality of bias controllers connected between the first wiring line and the second wiring line,
wherein each of the output buffer units includes a plurality of output buffers, each of the output buffers is connected to the first wiring line at a first node and to the second wiring line at a second node, each of the first and second nodes is at a different position or location along the first and second wiring lines, respectively, and each of the output buffer units includes (i) first bias transistors connected between the output buffers and the first nodes and (ii) second bias transistors connected between the output buffers and the second nodes, and
each of the bias controllers includes (i) a first transistor including a first source connected to the first wiring line, a first gate connected to gates of the first bias transistors, and a first drain connected to the first gate of the first transistor and (ii) a second transistor including a second source connected to the second wiring line, a second gate connected to gates of the second bias transistors, and a second drain connected to the second gate of the second transistor, and each of the bias controllers independently controls bias voltages of the plurality of output buffers in a corresponding one of the output buffer units.

15. The display driver according to claim 14 , wherein each of the bias controllers controls the bias voltages of each of the output buffers in a corresponding one of the output buffer units so as to receive a first bias voltage from a corresponding one of the first nodes and a second bias voltage from a corresponding one of the second nodes.

16. A display apparatus comprising:
a display panel including gate lines in rows, data lines in columns, and a pixel array connected to the gate lines and the data lines; and
display drivers configured to drive the gate lines and/or the data lines, wherein each of the display drivers includes:
an input pad configured to receive a supply voltage;
a wiring line connected to the input pad and configured to supply the supply voltage;
a digital-to-analog converter configured to convert digital data to analog signals;
a plurality of output buffer units configured to receive a bias voltage buffer the analog signals; and
a plurality of bias controllers connected to different positions of the wiring line,
wherein each of the bias controllers independently controls the bias voltage to a corresponding one of the output buffer units from the supply voltage supplied by the wiring line, a first one of the output buffer units and the wiring line are connected at a first node, a first bias controller corresponding to the first output buffer unit and the first wiring line are connected at a second node, and the first and second nodes are adjacent to each other.

Assignees

• Yeo Seung Jin
• Lee Sun Young
• Park Jeong Tae
• Dongbu Hitek Co Ltd

Inventors

• Yeo Seung Jin
• Lee Sun Young
• Park Jeong Tae

Classifications

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G3/3685 Primary

  Details of drivers for data electrodes · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title