Application processor sharing resource based on image resolution and devices including same

Patent metadata

Field	Value
Publication number	US-9858635-B2
Application number	US-201514845558-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Oct 7, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

An application processor includes a first scaler including a first vertical scaler and a first horizontal scaler, and a second scaler including a second vertical scaler and a second horizontal scaler, wherein the second vertical scaler is selectively shared between the first scaler and the second scaler in response to a determination of resolution for an image being processed.

First claim

What is claimed is:

1. An application processor comprising:
a first scaler including a first vertical scaler and a first horizontal scaler;
a second scaler including a second vertical scaler and a second horizontal scaler,
wherein the second vertical scaler is shared between the first scaler and the second scaler; and
a selection circuit that is configured to connect the second vertical scaler in parallel with the first vertical scaler, disconnect the second horizontal scaler from the second vertical scaler, and connect the first and second vertical scalers to the first horizontal scaler, in response to a selection signal generated based on a resolution of an image to be processed.

2. The application processor of claim 1 , further comprising:
a selection signal generation circuit that determines an image type for the image to be processed based on the resolution of the image, and generates the selection signal in response to the determination of the image type, wherein
in a first operating mode selected by the selection signal indicating a first image type, the selection circuit is configured to transmit a group of pixels corresponding to a first image of the first image type to the first vertical scaler, and in parallel, to transmit a group of pixels corresponding to a second image of the first image type to the second vertical scaler, and
in a second operating mode selected by the selection signal indicating a second image type, the selection circuit is configured to transmit a first group of pixels corresponding to a third image of the second type to the first vertical scaler, and also, transmit a second group of pixels corresponding to the third image to the second vertical scaler.

3. The application processor of claim 2 , further comprising:
a first direct memory access (DMA) controller configured to output at least one of the group of pixels corresponding to the first image, and the first and second groups of pixels corresponding to the third image; and
a second DMA controller configured to output the group of pixels corresponding to the second image.

4. The application processor of claim 2 , wherein the selection circuit in the first operating mode is further configured to output vertically scaled pixels provided by the first vertical scaler to the first horizontal scaler, and to output vertically scaled pixels provided by the second vertical scaler to the second horizontal scaler, and
the selection circuit in the second operating mode is configured to output vertically scaled pixels provided by the second vertical scaler to only the first horizontal scaler.

5. The application processor of claim 2 , wherein the selection signal generation circuit determines the first image type when the image to be processed has a first resolution, and determines the second image type when the image to be processed has a second resolution, greater than the first resolution.

6. The application processor of claim 2 , further comprising:
a first line memory configured to store at least one of the group of pixels corresponding to the first image, and a group of vertically scaled pixels received from the first vertical scaler; and
a second line memory configured to store at least one of the group of pixels corresponding to the second image, and a group vertically scaled pixels received from the second vertical scaler.

7. The application processor of claim 1 , wherein the first horizontal scaler has the largest pixel throughput among the first vertical scaler, the first horizontal scaler, the second vertical scaler, and the second horizontal scaler.

8. The application processor of claim 1 , further comprising:
a selection signal generation circuit that determines the image type for the image to be processed based on the resolution of the image, and generates selection information corresponding to the determination of image type,
wherein the selection circuit is selectively configured in response to the selection signal generated based on the selection information, wherein in a first operating mode selected by the selection signal indicating a first image type the selection circuit enables parallel and independent operation of the first vertical scaler and the second vertical scaler, together with parallel and independent operation of the first horizontal scaler and the second horizontal scaler, and
in a second operating mode selected by the selection signal indicating a second image type the selection circuit enables shared operation of the first vertical scaler and the second vertical scaler, together with operation of only the first horizontal scaler.

9. A system on chip comprising:
an image source that provides images including a first image, a second image, and a third image, each having one of a plurality of image types including a first image type and a second image type;
a first scaler including a first vertical scaler and a first horizontal scaler; and
a second scaler including a second vertical scaler and a second horizontal scaler,
wherein upon determining that the first image and the second image are respectively the first image type, the first vertical scaler vertically scales a first group of pixels corresponding to the first image, and in parallel, the second vertical scaler vertically scales a second group of pixels corresponding to the second image, and
upon determining that the third image is the second image type, the first vertical scaler together with the second vertical scaler vertically scale a third group of pixels corresponding to the third image.

10. The system on chip of claim 9 , wherein the first horizontal scaler horizontally scales vertically scaled pixels provided by the first vertical scaler together with vertically scaled pixels provided by the second vertical scaler.

11. The system on chip of claim 9 , further comprising:
a selection circuit that selectively connects the second vertical scaler with the first vertical scaler and disconnects the second horizontal scaler from the second vertical scaler in response to a selection signal indicating that an image received from the image source is the second image type.

12. The system on chip of claim 11 , further comprising:
a selection signal generation circuit that determines one of the plurality of image types for an image based on resolution of the image, and generates the selection signal corresponding to the determination of the image type,
wherein upon determining the first image type for the image, the selection circuit connects the first vertical scaler with the first horizontal scaler, and connects the second vertical scaler with the second horizontal scaler, and
upon determining the second image type for the image, the selection circuit connects the first vertical scaler and the second vertical scaler in parallel and connects the parallel combination of the first vertical scaler and the second vertical scaler to the first horizontal scaler, and disconnects the second horizontal scaler from the second vertical scaler.

13. The system on chip of claim 9 , further comprising:
a first direct memory access (DMA) controller that transmits the first group of pixels corresponding to the first image to the first vertical scaler, and transmits the third group of pixels corresponding to the third image to the first vertical scaler and the second vertical scaler; and
a second DMA controller that transmits the second group of pixels corresponding to the second image to the second vertical scaler.

14. The system on chip of claim 13 , wherein the first image and the second image respectively have a first resolution and the third image has a second re

Assignees

• Yoon Sang Chul
• Kim Seong Woon
• Lee Sang Hoon
• Samsung Electronics Co Ltd

Inventors

• Yoon Sang Chul
• Kim Seong Woon
• Lee Sang Hoon

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T3/4092

  Image resolution transcoding, e.g. by using client-server architectures · CPC title