Integrating manufacturing feedback into integrated circuit structure design

Patent metadata

Field	Value
Publication number	US-9858368-B2
Application number	US-201113182108-A
Country	US
Kind code	B2
Filing date	Jul 13, 2011
Priority date	Jul 13, 2011
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

First claim

What is claimed is:

1. A system comprising:
at least one computing device configured to integrate manufacturing feedback into an integrated circuit design by performing actions including:
defining an acceptable yield requirement for a first integrated circuit product;
obtaining manufacturing data about the first integrated circuit product,
wherein the obtaining of the manufacturing data includes performing a timing measurement on all logical paths in the first integrated circuit product;
performing a regression analysis on data representing the logical paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data,
wherein each of the plurality of parameter settings includes a parameter distribution having a bell curve;
determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement,
wherein the determining of the projection corner includes generating a yield curve for the first integrated circuit product as a function of a distribution of the timing measurement for all of the logical paths in the first integrated circuit product;
modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings,
wherein the modifying the design of the second integrated circuit product includes adjusting each of the bell curves of the plurality of parameter settings,
wherein adjusting each of the bell curves includes separate adjusting at least one of a width of the bell curve, a height of a peak of the bell curve, or a lateral position of the peak of the bell curve;
generating a second yield curve representing the design of the second integrated circuit product such that the second yield curve accounts for each of the adjusted bell curves;
performing a statistical timing closure of the modified design of the second integrated circuit product after the adjusting of each of the bell curves,
wherein the projection corner is a worst case corner that provides the slowest path delay between two nodes in a circuit path; and
manufacturing a physical chip in accuracy according to the design of the second integrated circuit product.

2. The system of claim 1 , wherein the acceptable yield requirement is based upon predetermined design yield.

3. The system of claim 1 , wherein the at least one computing device is further configured to provide the design of the second integrated circuit product.

4. The system of claim 1 , wherein the regression analysis includes at least one of: a parameter based analysis, a slack means and sigmas based analysis or a likelihood function analysis.

5. The system of claim 4 , wherein the regression analysis includes estimating sample values of the parameter settings prior to defining the plurality of parameter settings in the parameter based analysis.

6. The system of claim 1 , wherein the second integrated circuit product is formed subsequently to the first integrated circuit product.

7. The system of claim 1 , wherein the yield curve is adjusted for critical features by shifting the yield curve between a full chip timing yield of the first integrated circuit product in the worst corner scenario and a critical path yield of the first integrated circuit product.

8. The system of claim 1 , wherein the source of variation of the first integrated circuit product is a worst case parameter.

9. A computer program product comprising program code embodied in at least one non-transitory computer-readable medium, which when executed, enables a computer system to integrate manufacturing feedback into an integrated circuit design by performing actions comprising:
defining an acceptable yield requirement for a first integrated circuit product;
obtaining manufacturing data about the first integrated circuit product,
wherein the obtaining of the manufacturing data includes performing a timing measurement on all logical paths in the first integrated circuit product;
performing a regression analysis on data representing the logical paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data,
wherein each of the plurality of parameter settings includes a parameter distribution having a bell curve;
determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement,
wherein the determining of the projection corner includes generating a yield curve for the first integrated circuit product as a function of a distribution of the timing measurement for all of the logical paths in the first integrated circuit product;
modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings,
wherein the modifying the design of the second integrated circuit product includes adjusting each of the bell curves of the plurality of parameter settings,
wherein adjusting each of the bell curves includes separate adjusting at least one of a width of the bell curve, a height of a peak of the bell curve, or a lateral position of the peak of the bell curve;
generating a second yield curve representing the design of the second integrated circuit product such that the second yield curve accounts for each of the adjusted bell curves;
performing an at speed structural test on the modified design of the second integrated circuit product after adjusting each of the bell curves; and
wherein the projection corner is a worst case corner that provides the slowest path delay between two nodes in a circuit path; and
manufacturing a physical chip in accuracy according to the design of the second integrated circuit product.

10. The computer program of claim 9 , wherein the acceptable yield requirement is based upon predetermined design yield.

11. The computer program of claim 9 , wherein the regression analysis includes at least one of: a parameter based analysis, a slack means and sigmas based analysis or a likelihood function analysis.

12. The computer program of claim 11 , wherein the regression analysis includes estimating sample values of the parameter settings prior to defining the plurality of parameter settings in the parameter based analysis.

13. The computer program product of claim 9 , wherein the second integrated circuit product is formed subsequently to the first integrated circuit product.

14. The computer program product of claim 9 , wherein the yield curve is adjusted for critical features by shifting the yield curve between a full chip timing yield of the first integrated circuit product in a worst corner scenario and a critical path yield of the first integrated circuit product.

Assignees

• Buck Nathan C
• Dreibelbis Brian M
• Dubuque John P
• Foreman Eric A
• Habitz Peter A
• Hemmett Jeffrey G
• Venkateswaran Natesan
• Visweswariah Chandramouli
• Wang Xiaoyue
• Zolotov Vladmimir
• IBM

Inventors

• Buck Nathan C
• Dreibelbis Brian M
• Dubuque John P
• Foreman Eric A
• Habitz Peter A
• Hemmett Jeffrey G
• Venkateswaran Natesan
• Visweswariah Chandramouli
• Wang Xiaoyue
• Zolotov Vladmimir

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F17/5036 Primary

  Physics · mapped topic

• G06F2217/84

  Physics · mapped topic