System transparent retimer

Patent metadata

Field	Value
Publication number	US-9858234-B2
Application number	US-201514802957-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Jul 17, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

First claim

What is claimed is:

1. A method for managing an operational state of a retimer circuit included in an interconnect between a host system and a device system, the method comprising:
monitoring, during a first retimer operation state, a detection status of a first receiver included in the host system and coupled to a first port of the retimer circuit and a detection status of a second receiver included in a device system and coupled to a second port of the retimer circuit;
responsive to the detection status of the first receiver and the detection status of the second receiver indicating the presence of the first and second receivers, transitioning from the first retimer operation state to a second retimer operation state;
during the second retimer operation state:
monitoring at a first specified monitoring interval the detection status of the first receiver and the detection status of the second receiver,
detecting a control signal, wherein the detected control signal is associated with a ping message and a polling message,
decoding the polling message responsive to detecting the control signal in the absence of an occurrence of the ping message within the first specified monitoring interval, and
determining a link speed of the interconnect system based on the decoding; and

enabling a data path between the host system and the device system at the determined link speed.

2. The method of claim 1 , further comprising:
during the second retimer operation state, monitoring at a second specified monitoring interval the detection status of the first receiver and the detection status of the second receiver; and
transitioning from the second retimer operation state to the first retimer operation state when the detection status indicates that a receiver termination is not detected on the first or the second port within the second specified monitoring interval.

3. The method of claim 1 , further comprising:
during the second retimer operation state, monitoring at a second specified monitoring interval the detection status of the first receiver and detection status of the second receiver;
detecting the control signal; and
disabling monitoring the detection status responsive to detecting the control signal.

4. The method of claim 1 , wherein the interconnect system is a universal serial bus (USB) interconnect system.

5. The method of claim 4 , wherein the control signal is a low frequency periodic signal.

6. The method of claim 1 , further comprising:
determining whether a training bit is set;
responsive to determining that the training bit is set, training a clock data recovery circuit included in the retimer circuit; and
transitioning from the second retimer operating state to a third retimer operating state.

7. The method of claim 6 , further comprising:
detecting a loss of signal status for a threshold detecting period on the data path between the host system and the device system; and
disabling the data path between the host system and the device system.

8. A controller circuit for determining an operational state of a retimer circuit included in an interconnect between a host system and a device system, the controller circuit including instructions that when executed by the controller circuit cause the retimer to:
monitor, during a first retimer operation state, a detection status of a first receiver included in the host system and coupled to a first port of the retimer circuit and a detection status of a second receiver included in a device system and coupled to a second port of the retimer circuit;
responsive to the detection status of the first receiver and the detection status of the second receiver indicating the presence of the first and second receivers, transitioning from the first retimer operation state to a second retimer operation state;
during the second retimer operation state:
monitor at a first specified monitoring interval the detection status of the first receiver and the detection status of the second receiver,
detect a control signal, wherein the detected control signal is associated with a ping message and a polling message,
decode the polling message responsive to detecting the control signal in the absence of occurrence of the ping message within the first specified monitoring interval, and
determine a link speed of the interconnect system based on the decoding; and

enable a data path between the host system and the device system at the determined link speed.

9. The controller circuit of claim 8 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to:
during the second retimer operation state, monitor at a second specified monitoring interval the detection status of the first receiver and the detection status of the second receiver; and
transition from the second retimer operation state to the first retimer operation state when the detection status indicates that a receiver termination is not detected on the first or the second port within the second specified monitoring interval.

10. The controller circuit of claim 8 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to:
during the second retimer operation state, monitor at a second specified monitoring interval the detection status of the first receiver and detection status of the second receiver;
detect the control signal; and
disable monitoring the detection status responsive to detecting the control signal.

11. The controller circuit of claim 10 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to:
resume monitoring of the detection status when the control signal is not detected during the monitoring interval.

12. The controller circuit of claim 8 , wherein the interconnect system is a universal serial bus (USB) interconnect system.

13. The controller circuit of claim 8 , wherein the control signal is a low frequency periodic signal.

14. The controller circuit of claim 12 , wherein the polling message is Polling.LFPS.

15. The controller circuit of claim 12 , wherein the ping message is Ping.LFPS.

16. The controller circuit of claim 8 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to:
determine whether a training bit is set;
responsive to determining that the training bit is set, train a clock data recovery circuit included in the retimer circuit; and
transition from the second retimer operating state to a third retimer operating state.

17. The controller circuit of claim 16 , further comprising instructions that when executed by the controller circuit cause the retimer circuit to:
detect a loss of signal status for a threshold detecting period on the data path between the host system and the device system; and
disable the data path between the host system and the device system transitioning to a third retimer operating state.

Assignees

• Parade Tech Ltd

Inventors

• Chen Jian
• Qu Ming
• Lee Kc
• Yuan Zhengyu
• Ouyang Qing

Classifications

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F11/3051

  Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic