Register access control among multiple devices

Patent metadata

Field	Value
Publication number	US-9858222-B2
Application number	US-201414540414-A
Country	US
Kind code	B2
Filing date	Nov 13, 2014
Priority date	Nov 13, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the completion status of previous off-chip access requests, further off-chip access requests are selectively forwarded or suspended, while on-chip access request are sent independently of off-chip request status.

First claim

What is claimed is:

1. A circuit comprising:
a first plurality of ports for connecting to a plurality of on-chip devices via respective buses, a first bus of the respective buses configured to carry on-chip access requests, a second bus of the respective buses configured to carry off-chip access requests;
a second plurality of ports connecting to a master bus, the master bus further connecting to a control status register (CSR) and an off-chip device; and
a control circuit configured to:
detect a completion status of a first off-chip access request received from the second bus, the first off-chip access request being a request to access the off-chip device via the master bus;
selectively forward, based on the completion status, a second off-chip access request to the master bus the second off-chip access request being a request to access the off-chip device via the master bus; and
forward, to the master bus, an on-chip access request received from the first bus, the on-chip access request being a register master logic (RML) request to write to the CSR, the control circuit forwarding the on-chip access request independent of the completion status.

2. The circuit of claim 1 , further comprising an interface circuit connected to the control circuit via the master bus, the interface circuit configured to forward the first and second off-chip access requests to the off-chip device.

3. The circuit of claim 2 , wherein the interface circuit is further configured to update a register based on a signal received from the off-chip device, the register indicating the completion status.

4. The circuit of claim 2 , wherein the interface circuit is further configured to forward the completion status to the control circuit.

5. The circuit of claim 1 , wherein the control circuit is further configured to forward a backpressure signal to suspend access requests on the second bus based on the completion status.

6. The circuit of claim 1 , further comprising first and second buffers for receiving access requests via the first and second buses, respectively.

7. The circuit of claim 1 , further including a third bus of the respective buses, the third bus configured to carry on-chip access requests.

8. The circuit of claim 7 , wherein the control circuit is configured to order on-chip requests from the first, second and third buses based on a round-robin selection.

9. A method comprising:
receiving a plurality of on-chip access requests via a first bus;
receiving first and second off-chip access requests via a second bus;
forwarding the first off-chip access request to a control and status register (CSR) via a master bus;
detecting a completion status of the first off-chip access request received from the second bus, the first off-chip access request being a request to access the off-chip device via the master bus;
selectively forwarding, based on the completion status, a second off-chip access request to the master bus, the second off-chip access request being a request to access the off-chip device via the master bus; and
forwarding, to the CSR via the master bus, the plurality of on-chip access requests received from the first bus independent of the completion status the plurality of on-chip access requests being register master logic (RML) requests to write to the CSR.

10. The method of claim 9 , further comprising forwarding the first and second off-chip access requests to the off-chip device.

11. The method of claim 10 , further comprising updating a register based on a signal received from the off-chip device, the register indicating the completion status.

12. The method of claim 9 , further comprising forwarding a backpressure signal to suspend access requests on the second bus based on the completion status.

13. The method of claim 9 , further comprising receiving the access requests from the first and second buses to first and second buffers, respectively.

14. The method of claim 9 , further comprising receiving access requests from a third bus configured to carry on-chip access requests.

15. The method of claim 14 , further comprising ordering on-chip requests from the first, second and third buses based on a round-robin selection.

Assignees

• Cavium Inc

Inventors

• Sanzone Robert A
• Snyder Ii Wilson P
• Kessler Richard E

Classifications

• G06F13/37

  using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing · CPC title

• G06F13/364 Primary

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title