Computing architecture with concurrent programmable data co-processor

Patent metadata

Field	Value
Publication number	US-9858220-B2
Application number	US-201514660589-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Mar 17, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A coprocessor (PL) is disclosed. The PL includes a memory router, at least one collection block that is configured to transfer data to/from the memory router, each collection block includes a collection router that is configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block, and at least one programmable operator that is configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router.

First claim

The invention claimed is:

1. A coprocessor (PL) unit, comprising:
a memory router configured to i) transfer data to/from an external memory device, the transfer of data being initiated by an external processing system (PS) and ii) distribute the data to a plurality of blocks within the PL unit; and
at least one collection block configured to transfer data to/from the memory router, each collection block including
a collection router configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block,
at least one programmable operator configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router,

the PL unit configured to perform programmable operations on data transferred from the external memory and provide the operated-on data to the external memory with substantially zero overhead to the PS.

2. The PL unit of claim 1 , the at least one collection block further comprising:
at least one multiply-accumulator (MAC) block configured to i) transfer data to/from the collection router, ii) transfer data to/from the at least one programmable operator, and iii) perform multiply and accumulate operations on data received from the collection router and/or the at least one programmable operator.

3. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes max-pooling operations.

4. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes pixel-wise subtraction operations.

5. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes pixel-wise addition operations.

6. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes pixel-wise multiplication operations.

7. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes pixel-wise division operations.

8. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes non-linear operations.

9. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes MAC operations.

10. The PL unit of claim 1 , the programmable operation performed by the programmable operator includes non-linear operations.

11. The PL unit of claim 1 , the at least one collection unit is implemented based on field programmable gate array technology.

12. The PL unit of claim 1 , the at least one collection unit is implemented based on field programmable gate array (FPGA) technology.

13. The PL unit of claim 1 , the at least one collection unit is implemented based on application specific integrated circuit (ASIC) technology.

14. The PL unit of claim 1 , the PL unit includes a plurality of collection units.

15. The PL unit of claim 1 , the PL unit includes at least 50 collections units.

16. The PL unit of claim 1 , the PL unit includes at least 5 collections units.

17. The PL unit of claim 1 , the PL unit includes at least 5 collections units.

18. The PL unit of claim 2 , the collection router is further configured to transfer data to/from the at least one MAC.

19. The PL unit of claim 10 , the non-linear operations include applying a sigmoid function to a series.

20. The PL unit of claim 18 , the at least one programmable operator further configured to perform a programmable operation on data received from the at least one MAC.

Assignees

• Purdue Research Foundation

Inventors

• Culurciello Eugenio
• Martini Berin Eduard
• Gokhale Vinayak Anand
• Jin Jonghoon
• Dundar Aysegul

Classifications

• G06N3/063

  using electronic means · CPC title

• G06F2212/261

  Storage comprising a plurality of storage devices · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F9/46

  Multiprogramming arrangements · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title