Implementing cable failover in multiple cable PCI express IO interconnections

Patent metadata

Field	Value
Publication number	US-9858161-B2
Application number	US-201514924617-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

First claim

What is claimed is:

1. A computer system for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCI-Express or PCIE) IO interconnections attached to an IO drawer, comprising:
a processor;
system firmware provided with said processor;
a PCIE host bridge (PHB); said PHB connected to said processor;
multiple cable PCIE IO interconnections coupled between said PCIE host bridge (PHB) and an PCIE enclosure,
PCIE multiplexer logic coupled between said PHB and the multiple cable PCIE IO interconnections;
said processor using said system firmware for periodically implementing health check functions and responsive to a hardware interrupt to determine if the PCIE link is degraded and for detecting a degraded PCIE link; and
said processor using said system firmware for identifying a faulted low byte cable, and said processor using said system firmware and said PCIE multiplexer logic for performing a full lane reversal of the PCIE lanes including said processor issuing a Fundamental Reset, and PCIE clocks to said multiple cable PCIE IO interconnections from said PHB to said PCIE enclosure, deasserting said Fundamental Reset and retraining the PCIE links.

2. The system as recited in claim 1 , includes control code stored on a computer readable medium, wherein said control code comprising said system firmware.

3. The system as recited in claim 1 , wherein said processor using said system firmware for implementing health check functions for PCIE IO interconnections to identify a faulted low byte cable includes interrogating components to determine if a faulted low byte cable exists.

4. The system as recited in claim 3 , includes said processor using said system firmware for implementing health check functions for PCIE IO interconnections to identify a functional high byte cable.

5. The system as recited in claim 4 , includes said processor using said system firmware for interrogating components to determine if a functional high byte cable exists.

6. The system as recited in claim 1 , wherein said processor using said system firmware and said PCIE multiplexer logic for performing a full lane reversal of the PCIE lanes including said processor issuing said Fundamental Reset includes issuing a PCI Express ReSeT (PERST) to the PCIE IO interconnections.

7. The system as recited in claim 6 , includes said processor using said system firmware disabling the low byte cable.

8. The system as recited in claim 7 , includes said processor using said system firmware reconfiguring the PHB to reverse the PCIE lane order.

9. The system as recited in claim 1 , wherein said PCIE multiplexer logic coupled between said PHB and the multiple cable PCIE IO interconnections includes PCIE lane multiplexers to reverse the PCIE lane assignments from the PHB to the external PCIE cables and logic to control the PCIE lane multiplexers through system firmware.

Assignees

• IBM

Inventors

• Arroyo Jesse P
• Engel Christopher J
• Naderi Kaveh
• Smith James E

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F11/2017 Primary

  where memory access, memory control or I/O control functionality is redundant (redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089) · CPC title

• G06F11/1616 Primary

  where the redundant component is an I/O device or an adapter therefor · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/2007

  using redundant communication media · CPC title